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Searched refs:Q_ADDR (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
H A Dsky2.c1078 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset()
1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset()
1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset()
1081 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset()
1275 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum()
1306 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_rss()
1309 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_rss()
1339 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); in sky2_rx_stop()
1529 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start()
1535 sky2_write32(hw, Q_ADDR(rx in sky2_rx_start()
[all...]
H A Dskge.c2521 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset()
2522 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset()
2523 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset()
2524 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset()
2608 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); in skge_up()
2639 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop()
2642 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop()
2680 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down()
2694 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down()
2818 skge_write8(hw, Q_ADDR(txqadd in skge_xmit_frame()
[all...]
H A Dskge.h456 /* Queue Register Offsets, use Q_ADDR() to access */
476 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro
H A Dsky2.h727 /* Queue Register Offsets, use Q_ADDR() to access */
751 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/
H A Dsky2.c1077 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset()
1078 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset()
1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset()
1080 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset()
1274 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum()
1305 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_rss()
1308 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_rss()
1338 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); in sky2_rx_stop()
1528 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); in sky2_rx_start()
1535 sky2_write32(hw, Q_ADDR(rx in sky2_rx_start()
[all...]
H A Dskge.c2528 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset()
2529 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset()
2530 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset()
2531 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset()
2615 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); in skge_up()
2646 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop()
2649 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop()
2687 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down()
2701 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down()
2825 skge_write8(hw, Q_ADDR(txqadd in skge_xmit_frame()
[all...]
H A Dskge.h456 /* Queue Register Offsets, use Q_ADDR() to access */
476 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro
H A Dsky2.h727 /* Queue Register Offsets, use Q_ADDR() to access */
751 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro

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