Searched refs:PWR_CTRL (Results 1 - 4 of 4) sorted by relevance
| /kernel/linux/linux-5.10/drivers/clk/nxp/ |
| H A D | clk-lpc32xx.c | 106 /* Only one control PWR_CTRL[10] for both muxes */
110 /* Only one control PWR_CTRL[2] for all three muxes */
1234 /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
1235 LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
1237 LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
1239 LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
1241 /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
1242 LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
1244 LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
1247 /* 3 always on gates with a single control PWR_CTRL[
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/nxp/ |
| H A D | clk-lpc32xx.c | 106 /* Only one control PWR_CTRL[10] for both muxes */
110 /* Only one control PWR_CTRL[2] for all three muxes */
1234 /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
1235 LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
1237 LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
1239 LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
1241 /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
1242 LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
1244 LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
1247 /* 3 always on gates with a single control PWR_CTRL[
[all...] |
| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| H A D | clk-exynos5260.h | 88 #define PWR_CTRL 0x1020 macro
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| H A D | clk-exynos5260.h | 88 #define PWR_CTRL 0x1020 macro
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