Lines Matching refs:PWR_CTRL
106 /* Only one control PWR_CTRL[10] for both muxes */
110 /* Only one control PWR_CTRL[2] for all three muxes */
1234 /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
1235 LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
1237 LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
1239 LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
1241 /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
1242 LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
1244 LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
1247 /* 3 always on gates with a single control PWR_CTRL[0] same as OSC */
1248 LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1249 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1250 LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),