Home
last modified time | relevance | path

Searched refs:PWM (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-lpss.c3 * Intel Low Power Subsystem PWM controller driver
23 #define PWM 0x00000000 macro
29 /* Size of each PWM register space if multiple */
41 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_read()
48 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_write()
54 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM; in pwm_lpss_wait_for_update()
60 * PWM Configuration register has SW_UPDATE bit that is set when a new in pwm_lpss_wait_for_update()
65 * the bit enabled, PWM may freeze. That is, while one can still write in pwm_lpss_wait_for_update()
237 dev_err(dev, "failed to add PWM chip: %d\n", ret); in pwm_lpss_probe()
263 MODULE_DESCRIPTION("PWM drive
[all...]
/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-lpss.c3 * Intel Low Power Subsystem PWM controller driver
26 #define PWM 0x00000000 macro
32 /* Size of each PWM register space if multiple */
78 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_read()
85 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); in pwm_lpss_write()
91 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM; in pwm_lpss_wait_for_update()
97 * PWM Configuration register has SW_UPDATE bit that is set when a new in pwm_lpss_wait_for_update()
102 * the bit enabled, PWM may freeze. That is, while one can still write in pwm_lpss_wait_for_update()
277 dev_err(dev, "failed to add PWM chip: %d\n", ret); in devm_pwm_lpss_probe()
291 MODULE_DESCRIPTION("PWM drive
[all...]
/kernel/linux/linux-5.10/drivers/pinctrl/
H A Dpinctrl-ocelot.c190 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
254 JAGUAR2_P(23, PWM, NONE);
400 SPARX5_P(23, PWM, UART3, TWI_SCL_M);
407 SPARX5_P(30, SG2, SI, PWM);
H A Dpinctrl-palmas.c313 FUNCTION_GROUP(pwm, PWM), \
477 PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
478 PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
/kernel/linux/linux-6.6/drivers/pinctrl/
H A Dpinctrl-ocelot.c385 LUTON_P(29, PWM, NONE);
443 SERVAL_P(5, PWM, NONE, NONE);
541 OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
605 JAGUAR2_P(23, PWM, NONE);
745 SERVALT_P(17, PWM, NONE, TWI_SCL_M);
843 SPARX5_P(23, PWM, UART3, TWI_SCL_M);
850 SPARX5_P(30, SG2, SI, PWM);
H A Dpinctrl-palmas.c299 FUNCTION_GROUP(pwm, PWM), \
463 PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
464 PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
/kernel/linux/linux-5.10/drivers/pinctrl/tegra/
H A Dpinctrl-tegra20.c2074 MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
2131 MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
2132 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
2133 MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
2154 MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
/kernel/linux/linux-6.6/drivers/pinctrl/tegra/
H A Dpinctrl-tegra20.c2071 MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
2128 MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
2129 MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
2130 MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
2151 MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),

Completed in 14 milliseconds