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Searched refs:PP_CONTROL (Results 1 - 24 of 24) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dpsb_lid.c28 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
44 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
H A Dpsb_intel_lvds.c221 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
266 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); in psb_intel_lvds_save()
317 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); in psb_intel_lvds_restore()
321 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore()
327 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) in psb_intel_lvds_restore()
[all...]
H A Dcdv_intel_dp.c392 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
395 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on()
396 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
406 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
409 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off()
410 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
425 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
429 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on()
430 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
450 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
[all...]
H A Dcdv_intel_lvds.c115 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
126 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
H A Doaktrail_lvds.c46 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
57 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
H A Doaktrail_device.c233 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); in oaktrail_save_display_registers()
262 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers()
370 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); in oaktrail_restore_display_registers()
H A Dcdv_device.c278 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); in cdv_save_display_registers()
357 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); in cdv_restore_display_registers()
H A Dpsb_intel_reg.h168 #define PP_CONTROL 0x61204 macro
834 /* #define PP_CONTROL 0x61204 */
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Dpsb_lid.c28 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
44 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
H A Dpsb_intel_lvds.c220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
231 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
264 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); in psb_intel_lvds_save()
315 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); in psb_intel_lvds_restore()
319 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore()
325 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) in psb_intel_lvds_restore()
[all...]
H A Dcdv_intel_dp.c388 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
391 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on()
392 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
402 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
405 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off()
406 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
421 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
425 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on()
426 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
446 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
[all...]
H A Doaktrail_lvds.c48 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
59 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
H A Dcdv_intel_lvds.c117 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
128 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
H A Doaktrail_device.c175 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); in oaktrail_save_display_registers()
204 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers()
312 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); in oaktrail_restore_display_registers()
H A Dcdv_device.c253 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); in cdv_save_display_registers()
336 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); in cdv_restore_display_registers()
H A Dpsb_intel_reg.h168 #define PP_CONTROL 0x61204 macro
794 /* #define PP_CONTROL 0x61204 */
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c158 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
206 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
211 intel_de_write(dev_priv, PP_CONTROL(0), val); in intel_lvds_pps_init_hw()
317 intel_de_write(dev_priv, PP_CONTROL(0), in intel_enable_lvds()
318 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
336 intel_de_write(dev_priv, PP_CONTROL(0), in intel_disable_lvds()
337 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); in intel_disable_lvds()
H A Dintel_dp.c990 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
1120 regs->pp_ctrl = PP_CONTROL(pps_idx); in intel_pps_get_registers()
1125 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ in intel_pps_get_registers()
1171 pp_ctrl_reg = PP_CONTROL(pipe); in edp_notify_handler()
3043 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in edp_panel_vdd_on()
3112 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in edp_panel_vdd_off_sync()
H A Dintel_display.c1221 pp_reg = PP_CONTROL(0); in assert_panel_unlocked()
1243 pp_reg = PP_CONTROL(pipe); in assert_panel_unlocked()
1248 pp_reg = PP_CONTROL(0); in assert_panel_unlocked()
16866 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)); in intel_pps_unlock_regs_wa()
16869 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val); in intel_pps_unlock_regs_wa()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c164 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
212 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
217 intel_de_write(dev_priv, PP_CONTROL(0), val); in intel_lvds_pps_init_hw()
324 intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); in intel_enable_lvds()
342 intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0); in intel_disable_lvds()
H A Dintel_pps_regs.h48 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) macro
H A Dintel_pps.c280 return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD; in pps_has_vdd_on()
494 regs->pp_ctrl = PP_CONTROL(pps_idx); in intel_pps_get_registers()
499 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ in intel_pps_get_registers()
567 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_check_power_unlocked()
601 "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in wait_panel_status()
611 "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in wait_panel_status()
753 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_on_unlocked()
825 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_off_sync_unlocked()
1660 intel_de_rmw(dev_priv, PP_CONTROL(pps_idx), in intel_pps_unlock_regs_wa()
1687 pp_reg = PP_CONTROL( in assert_pps_unlocked()
[all...]
H A Dintel_dsi_vbt.c429 intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON, in icl_native_gpio_set_value()
436 intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE, in icl_native_gpio_set_value()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_reg.h5031 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) macro

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