Home
last modified time | relevance | path

Searched refs:PMC (Results 1 - 24 of 24) sorted by relevance

/kernel/linux/linux-5.10/drivers/video/fbdev/riva/
H A Dnvreg.h126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mas
[all...]
H A Dnv_driver.c167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
281 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
282 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
330 par->riva.PMC = in riva_common_setup()
H A Driva_hw.c1399 LOAD_FIXED_STATE(Riva,PMC); in LoadStateExt()
1553 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1554 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1555 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1556 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1557 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1558 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1559 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1711 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1968 if (((NV_RD32(chip->PMC, in nv3GetConfig()
[all...]
H A Driva_hw.h452 volatile U032 __iomem *PMC; member
H A Dfbdev.c303 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; in riva_bl_update_status()
311 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); in riva_bl_update_status()
/kernel/linux/linux-6.6/drivers/video/fbdev/riva/
H A Dnvreg.h126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mas
[all...]
H A Dnv_driver.c167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
281 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
282 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
330 par->riva.PMC = in riva_common_setup()
H A Driva_hw.c1379 LOAD_FIXED_STATE(Riva,PMC); in LoadStateExt()
1533 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1534 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1535 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1536 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1537 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1538 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1539 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1691 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1948 if (((NV_RD32(chip->PMC, in nv3GetConfig()
[all...]
H A Driva_hw.h452 volatile U032 __iomem *PMC; member
H A Dfbdev.c298 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; in riva_bl_update_status()
306 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); in riva_bl_update_status()
/kernel/linux/linux-6.6/drivers/perf/
H A Dfsl_imx9_ddr_perf.c36 #define PMC(n) (0x40 + 0x18 + (0x10 * n)) macro
274 writel(0, pmu->base + PMC(counter) + 0x4); in ddr_perf_clear_counter()
275 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
277 writel(0, pmu->base + PMC(counter)); in ddr_perf_clear_counter()
287 val = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
293 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4); in ddr_perf_read_counter()
294 val_lower = readl_relaxed(pmu->base + PMC(counter)); in ddr_perf_read_counter()
295 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4)); in ddr_perf_read_counter()
/kernel/linux/linux-5.10/drivers/video/fbdev/nvidia/
H A Dnv_backlight.c63 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
76 NV_WR32(par->PMC, 0x10F0, tmp_pmc); in nvidia_bl_update_status()
H A Dnv_hw.c147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
950 NV_WR32(par->PMC, 0x0140, 0x00000000); in NVLoadStateExt()
951 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF); in NVLoadStateExt()
952 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF); in NVLoadStateExt()
1266 NV_WR32(par->PMC, 0x1700, in NVLoadStateExt()
1268 NV_WR32(par->PMC, 0x1704, 0); in NVLoadStateExt()
1269 NV_WR32(par->PMC, in NVLoadStateExt()
[all...]
H A Dnv_setup.c237 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { in nv10GetConfig()
238 NV_WR32(par->PMC, 0x0004, 0x01000001); in nv10GetConfig()
306 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
H A Dnv_type.h164 volatile u32 __iomem *PMC; member
/kernel/linux/linux-6.6/drivers/video/fbdev/nvidia/
H A Dnv_backlight.c57 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
70 NV_WR32(par->PMC, 0x10F0, tmp_pmc); in nvidia_bl_update_status()
H A Dnv_hw.c147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
950 NV_WR32(par->PMC, 0x0140, 0x00000000); in NVLoadStateExt()
951 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF); in NVLoadStateExt()
952 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF); in NVLoadStateExt()
1266 NV_WR32(par->PMC, 0x1700, in NVLoadStateExt()
1268 NV_WR32(par->PMC, 0x1704, 0); in NVLoadStateExt()
1269 NV_WR32(par->PMC, in NVLoadStateExt()
[all...]
H A Dnv_setup.c234 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { in nv10GetConfig()
235 NV_WR32(par->PMC, 0x0004, 0x01000001); in nv10GetConfig()
303 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
H A Dnv_type.h164 volatile u32 __iomem *PMC; member
/kernel/linux/linux-5.10/arch/sparc/include/asm/
H A Dns87303.h20 #define PMC 0x06 macro
/kernel/linux/linux-6.6/arch/sparc/include/asm/
H A Dns87303.h20 #define PMC 0x06 macro
/kernel/linux/linux-6.6/drivers/pinctrl/renesas/
H A Dpinctrl-rzg2l.c94 #define PMC(n) (0x0200 + 0x10 + (n)) macro
176 /* Temporarily switch to GPIO mode with PMC register */ in rzg2l_pinctrl_set_pfc_mode()
177 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
178 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
193 /* Switch to Peripheral pin function with PMC register */ in rzg2l_pinctrl_set_pfc_mode()
194 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
195 writeb(reg | BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
810 /* Select GPIO mode in PMC Register */ in rzg2l_gpio_request()
811 reg8 = readb(pctrl->base + PMC(port)); in rzg2l_gpio_request()
813 writeb(reg8, pctrl->base + PMC(por in rzg2l_gpio_request()
[all...]
/kernel/linux/linux-5.10/arch/arm/mm/
H A Dproc-v7.S238 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
250 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
/kernel/linux/linux-6.6/arch/arm/mm/
H A Dproc-v7.S240 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
252 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC

Completed in 27 milliseconds