PLL_INT (reference) in projects: kernel - OpenGrok search results

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Searched refs:PLL_INT (Results 1 - 5 of 5) sorted by relevance

/kernel/linux/linux-5.10/sound/pci/ctxfi/
H A D	cthardware.h	`202 #define PLL_INT (1 << 10) /* PLL input-clock out-of-range */ macro`
/kernel/linux/linux-6.6/sound/pci/ctxfi/
H A D	cthardware.h	`202 #define PLL_INT (1 << 10) /* PLL input-clock out-of-range */ macro`
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
H A D	chipone-icn6211.c	`84 #define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 / macro 273 M is integer multiplier, register PLL_INT(0) is multiplier in chipone_configure_pll() 340 chipone_writeb(icn, PLL_INT(0), best_m); in chipone_configure_pll()`
/kernel/linux/linux-5.10/drivers/net/ieee802154/
H A D	mcr20a.c	`79 static const u8 PLL_INT[16] = { variable 500 /* freqency = ((PLL_INT+64) + (PLL_FRAC/65536)) * 32 MHz */ in mcr20a_set_channel() 501 ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]); in mcr20a_set_channel()`
/kernel/linux/linux-6.6/drivers/net/ieee802154/
H A D	mcr20a.c	`79 static const u8 PLL_INT[16] = { variable 500 /* freqency = ((PLL_INT+64) + (PLL_FRAC/65536)) * 32 MHz */ in mcr20a_set_channel() 501 ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]); in mcr20a_set_channel()`

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