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Searched refs:PIPECONF (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
185 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &= in emulate_monitor_status_change()
246 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE; in emulate_monitor_status_change()
504 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
H A Dhandlers.c2040 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2041 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2042 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2043 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dicl_dsi.c996 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_enable_transcoder()
998 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_enable_transcoder()
1001 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_enable_transcoder()
1222 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_disable_transcoder()
1224 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_disable_transcoder()
1227 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_disable_transcoder()
1627 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_get_hw_state()
H A Dintel_color.c480 val = intel_de_read(dev_priv, PIPECONF(pipe)); in i9xx_color_commit()
483 intel_de_write(dev_priv, PIPECONF(pipe), val); in i9xx_color_commit()
493 val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_color_commit()
496 intel_de_write(dev_priv, PIPECONF(pipe), val); in ilk_color_commit()
H A Dintel_display.c1094 i915_reg_t reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in assert_pipe()
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_enable_pch_transcoder()
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
1882 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()
1923 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()
5492 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_pll_enable()
5562 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_disable()
5589 /* BPC in FDI rx is consistent with that in PIPECONF */ in ilk_fdi_disable()
5591 temp |= (intel_de_read(dev_priv, PIPECONF(pip in ilk_fdi_disable()
[all...]
H A Dintel_crt.c697 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
H A Dintel_display_power.c1248 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1250 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1264 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1265 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
H A Dintel_dp.c2485 * some conflicting bits in PIPECONF which will mess up in intel_dp_limited_color_range()
5523 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_disable()
5531 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_disable()
5550 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_enable()
5558 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_enable()
7277 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); in intel_dp_set_drrs_state()
H A Dvlv_dsi.c1035 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_reg.h6008 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) macro

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