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Searched refs:MUX_GATE_CLR_SET_UPD (Results 1 - 17 of 17) sorted by relevance

/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-mt8188-topckgen.c969 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
971 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
973 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
975 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
978 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
980 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
982 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
984 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
987 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
989 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP
[all...]
H A Dclk-mt8195-topckgen.c877 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
879 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
881 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
883 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
886 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
888 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
890 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
892 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
895 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
897 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP
[all...]
H A Dclk-mt8186-topckgen.c511 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
513 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
516 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1, "top_camtg1",
518 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
520 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
522 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
525 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
527 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6, "top_camtg6",
529 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
531 MUX_GATE_CLR_SET_UPD(CLK_TOP_SP
[all...]
H A Dclk-mt7986-topckgen.c175 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
177 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
190 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
200 MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
220 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SE
[all...]
H A Dclk-mt7981-topckgen.c292 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
294 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
296 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
298 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
301 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
303 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
305 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
307 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
338 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
342 MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SE
[all...]
H A Dclk-mt8192.c554 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
560 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
562 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
564 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
566 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
569 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
571 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
573 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
575 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
578 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SE
[all...]
H A Dclk-mt6779.c642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
644 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
647 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP
[all...]
H A Dclk-mt8365.c413 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
415 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
417 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
420 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
422 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
424 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
426 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
429 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
431 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
449 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SE
[all...]
H A Dclk-mt8183.c462 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
464 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
466 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
469 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
471 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
473 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
475 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
478 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
480 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
482 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMT
[all...]
H A Dclk-mt7981-infracfg.c47 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
50 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
53 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
56 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
59 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
62 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
65 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
68 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
71 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
74 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSE
[all...]
H A Dclk-mt7986-infracfg.c40 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
43 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
46 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
49 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
52 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
55 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
58 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
61 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
65 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
H A Dclk-mt6765.c376 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
379 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
383 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
386 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
389 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
392 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
396 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
399 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
402 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
405 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SE
[all...]
H A Dclk-mux.h70 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ macro
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mt6779.c642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
644 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
647 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP
[all...]
H A Dclk-mt8183.c528 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
531 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
534 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
538 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
541 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
544 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
547 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
551 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
554 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
557 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMT
[all...]
H A Dclk-mt6765.c373 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
376 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
380 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
383 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
386 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
389 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
393 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
396 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
399 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
402 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SE
[all...]
H A Dclk-mux.h72 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ macro

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