MPLL_FREQ_LEVEL_0 (reference) in projects: kernel - OpenGrok search results

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Searched refs:MPLL_FREQ_LEVEL_0 (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	rv6xxd.h	`78 #define MPLL_FREQ_LEVEL_0 0x6e8 macro`
H A D	rv6xx_dpm.c	373 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_enable_post_divider() 376 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); in rv6xx_memory_clock_entry_enable_post_divider() 382 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_post_divider() 389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), in rv6xx_memory_clock_entry_set_feedback_divider() 396 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_reference_divider()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	rv6xxd.h	`78 #define MPLL_FREQ_LEVEL_0 0x6e8 macro`
H A D	rv6xx_dpm.c	373 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_enable_post_divider() 376 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); in rv6xx_memory_clock_entry_enable_post_divider() 382 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_post_divider() 389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), in rv6xx_memory_clock_entry_set_feedback_divider() 396 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_reference_divider()

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