/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/ |
H A D | cik_regs.h | 69 #define GRBM_GFX_INDEX 0x30800 macro
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H A D | kfd_dbgdev.c | 653 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; in dbgdev_wave_control_diq() 667 /* Restore the GRBM_GFX_INDEX register */ in dbgdev_wave_control_diq() 677 GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE; in dbgdev_wave_control_diq()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/ |
H A D | cik_regs.h | 69 #define GRBM_GFX_INDEX 0x30800 macro
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_amdkfd_gfx_v8.c | 553 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 555 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 557 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
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H A D | gfx_v9_4.c | 99 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_select_se_sh() 102 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_select_se_sh() 106 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_select_se_sh() 109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh() 112 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_select_se_sh() 115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
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H A D | amdgpu_amdkfd_gfx_v10_3.c | 600 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3() 602 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3() 604 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
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H A D | vce_v4_0.c | 736 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE 748 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 753 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10); 758 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 940 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i); 959 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
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H A D | amdgpu_amdkfd_gfx_v10.c | 688 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 690 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 692 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
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H A D | amdgpu_amdkfd_gfx_v11.c | 585 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11() 587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11() 589 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11()
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H A D | gfx_v9_4_2.c | 855 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_2_select_se_sh() 858 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_2_select_se_sh() 862 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh() 865 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_2_select_se_sh() 868 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh() 871 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
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H A D | amdgpu_amdkfd_gfx_v9.c | 640 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute() 642 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute() 644 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
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H A D | soc15_common.h | 158 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \
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H A D | gfx_v9_4_3.c | 529 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh() 532 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh() 536 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh() 539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_3_xcc_select_se_sh() 542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh() 545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_3_xcc_select_se_sh()
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H A D | vce_v3_0.c | 639 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE in vce_v3_0_check_soft_reset() 851 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v9_4.c | 99 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_select_se_sh() 102 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_select_se_sh() 106 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_select_se_sh() 109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh() 112 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_select_se_sh() 115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
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H A D | amdgpu_amdkfd_gfx_v10.c | 723 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 725 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
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H A D | amdgpu_amdkfd_gfx_v8.c | 590 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 592 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 594 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
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H A D | vce_v4_0.c | 700 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE 712 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 717 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10); 722 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 904 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i); 923 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
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H A D | amdgpu_amdkfd_gfx_v9.c | 671 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute() 673 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute() 675 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
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H A D | amdgpu_amdkfd_gfx_v10_3.c | 633 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3() 635 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3() 637 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
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H A D | vce_v3_0.c | 612 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE in vce_v3_0_check_soft_reset() 824 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
H A D | cypress_dpm.c | 127 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable() 154 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable() 188 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable() 209 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
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H A D | ni.c | 1095 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init() 1115 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init() 1124 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
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/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
H A D | cypress_dpm.c | 125 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable() 152 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable() 186 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable() 207 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
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H A D | ni.c | 1082 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init() 1102 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init() 1111 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
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