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Searched refs:FORMAT_CONTROL (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp.c113 REG_SET_2(FORMAT_CONTROL, 0, in dpp2_cnv_setup()
118 //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14 in dpp2_cnv_setup()
119 //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled in dpp2_cnv_setup()
120 //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled in dpp2_cnv_setup()
121 //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled in dpp2_cnv_setup()
122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
223 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_E in dpp2_cnv_setup()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp.c113 REG_SET_2(FORMAT_CONTROL, 0, in dpp2_cnv_setup()
118 //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14 in dpp2_cnv_setup()
119 //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled in dpp2_cnv_setup()
120 //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled in dpp2_cnv_setup()
121 //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled in dpp2_cnv_setup()
122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
227 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_E in dpp2_cnv_setup()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_dpp.c60 REG_SET_2(FORMAT_CONTROL, 0, in dpp201_cnv_setup()
64 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp201_cnv_setup()
65 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp201_cnv_setup()
66 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp201_cnv_setup()
67 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp201_cnv_setup()
168 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp201_cnv_setup()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.c193 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
197 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp3_cnv_setup()
198 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp3_cnv_setup()
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp3_cnv_setup()
200 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp3_cnv_setup()
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp3_cnv_setup()
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp3_cnv_setup()
204 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp3_cnv_setup()
307 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
H A Ddcn30_dpp.h134 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_ipp.h35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
168 uint32_t FORMAT_CONTROL; member
H A Ddcn10_dpp.c311 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
317 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
388 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
H A Ddcn10_dpp_cm.c714 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
H A Ddcn10_dpp.h117 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
1330 uint32_t FORMAT_CONTROL; \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp.c304 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
310 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
382 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
H A Ddcn10_ipp.h35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
189 uint32_t FORMAT_CONTROL; member
H A Ddcn10_dpp_cm.c714 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
H A Ddcn10_dpp.h120 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
1342 uint32_t FORMAT_CONTROL; \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.c192 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup()
196 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp3_cnv_setup()
197 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp3_cnv_setup()
198 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp3_cnv_setup()
199 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp3_cnv_setup()
201 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); in dpp3_cnv_setup()
202 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); in dpp3_cnv_setup()
203 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); in dpp3_cnv_setup()
310 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
H A Ddcn30_dpp.h135 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h522 SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \

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