Home
last modified time | relevance | path

Searched refs:DDR (Results 1 - 19 of 19) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-mb86s7x.c31 #define DDR(x) (0x10 + x / 8 * 4) macro
83 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
85 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
108 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
110 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-mb86s7x.c31 #define DDR(x) (0x10 + x / 8 * 4) macro
83 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
85 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
108 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
110 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
H A Dsleep24xx.S37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
69 /* The DPLL has to be on before we take the DDR out of self refresh */
75 movs r0, r0 @ see if DDR or SDR
H A Dsram242x.S80 /* set up for return, DDR should be good */
131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
175 /* With DDR, we need to take care of the DLL for the frequency change */
228 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
H A Dsram243x.S80 /* set up for return, DDR should be good */
131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
175 /* With DDR, we need to take care of the DLL for the frequency change */
228 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
H A Dsleep24xx.S37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
69 /* The DPLL has to be on before we take the DDR out of self refresh */
75 movs r0, r0 @ see if DDR or SDR
H A Dsram242x.S80 /* set up for return, DDR should be good */
131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
175 /* With DDR, we need to take care of the DLL for the frequency change */
228 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
H A Dsram243x.S80 /* set up for return, DDR should be good */
131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
175 /* With DDR, we need to take care of the DLL for the frequency change */
228 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
/kernel/linux/linux-5.10/drivers/pinctrl/tegra/
H A Dpinctrl-tegra30.c2203 PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y),
2204 PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y),
2205 PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y),
2262 PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y),
2263 PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y),
2264 PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y),
2265 PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y),
2266 PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y),
2267 PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y),
2268 PINGROUP(vi_d8_pl6, DDR, SDMMC
[all...]
/kernel/linux/linux-6.6/drivers/pinctrl/tegra/
H A Dpinctrl-tegra30.c2200 PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y),
2201 PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y),
2202 PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y),
2259 PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y),
2260 PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y),
2261 PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y),
2262 PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y),
2263 PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y),
2264 PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y),
2265 PINGROUP(vi_d8_pl6, DDR, SDMMC
[all...]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h306 * d: DDR, PCI, LIO
321 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
323 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h297 * d: DDR, PCI, LIO
312 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
314 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
/kernel/linux/linux-6.6/drivers/clk/at91/
H A Dsama7g5.c42 * @PLL_ID_DDR: DDR PLL identifier
238 * This feeds ddrpll_divpmcck which feeds DDR. It should not
250 /* This feeds DDR. It should not be disabled. */
394 .ep = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), },
402 .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(DDR, DIV0),
589 .pp = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), },
/kernel/linux/linux-5.10/arch/arm/mach-tegra/
H A Dsleep-tegra20.S341 bne emcself @ loop until DDR in self-refresh
H A Dsleep-tegra30.S808 bne emcself @ loop until DDR in self-refresh
/kernel/linux/linux-6.6/arch/arm/mach-tegra/
H A Dsleep-tegra20.S370 bne emcself @ loop until DDR in self-refresh
H A Dsleep-tegra30.S864 bne emcself @ loop until DDR in self-refresh
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Domap_hsmmc.c97 #define DDR (1 << 19) macro
562 * - Controller should not be using DDR Mode in omap_hsmmc_set_clock()
591 con |= DDR; /* configure in DDR mode */ in omap_hsmmc_set_bus_width()
593 con &= ~DDR; in omap_hsmmc_set_bus_width()
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Domap_hsmmc.c97 #define DDR (1 << 19) macro
562 * - Controller should not be using DDR Mode in omap_hsmmc_set_clock()
591 con |= DDR; /* configure in DDR mode */ in omap_hsmmc_set_bus_width()
593 con &= ~DDR; in omap_hsmmc_set_bus_width()

Completed in 20 milliseconds