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Searched refs:CSR0_STRT (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/amd/
H A Dsun3lance.c213 #define CSR0_STRT 0x0002 /* start (RS) */ macro
443 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA; in lance_open()
561 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_start_xmit()
593 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT; in lance_start_xmit()
637 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; in lance_start_xmit()
712 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()
750 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()
923 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()
H A Datarilance.c21 following AMD, CSR0_STRT should be set only after IDON is detected
313 #define CSR0_STRT 0x0002 /* start (RS) */ macro
669 DREG = CSR0_STRT; in lance_open()
766 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_tx_timeout()
873 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP | in lance_interrupt()
908 DREG = CSR0_STRT; in lance_interrupt()
946 DREG = CSR0_STRT; in lance_interrupt()
1108 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()
H A Dni65.h33 #define CSR0_STRT 0x0002 /* Start (RS) */ macro
H A Dam79c961a.h29 #define CSR0_STRT 0x0002 macro
H A Dni65.c761 writedatareg(CSR0_STRT | csr0); in ni65_stop_start()
783 writedatareg(CSR0_STRT | csr0); in ni65_stop_start()
858 writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT); in ni65_lance_reinit()
H A Dam79c961a.c299 write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT); in am79c961_init_for_open()
/kernel/linux/linux-6.6/drivers/net/ethernet/amd/
H A Dsun3lance.c213 #define CSR0_STRT 0x0002 /* start (RS) */ macro
437 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA; in lance_open()
555 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_start_xmit()
587 REGA( CSR0 ) = CSR0_INIT | CSR0_STRT; in lance_start_xmit()
631 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; in lance_start_xmit()
706 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()
744 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()
917 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()
H A Datarilance.c21 following AMD, CSR0_STRT should be set only after IDON is detected
313 #define CSR0_STRT 0x0002 /* start (RS) */ macro
668 DREG = CSR0_STRT; in lance_open()
765 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_tx_timeout()
872 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP | in lance_interrupt()
907 DREG = CSR0_STRT; in lance_interrupt()
945 DREG = CSR0_STRT; in lance_interrupt()
1107 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()

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