| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 116 #define CLK_TOP_AUD_1_SEL 105 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mt8173-clk.h | 119 #define CLK_TOP_AUD_1_SEL 109 macro
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| H A D | mt6765-clk.h | 148 #define CLK_TOP_AUD_1_SEL 113 macro
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| H A D | mt2712-clk.h | 156 #define CLK_TOP_AUD_1_SEL 125 macro
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| H A D | mt8192-clk.h | 59 #define CLK_TOP_AUD_1_SEL 47 macro
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| /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 116 #define CLK_TOP_AUD_1_SEL 105 macro
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| H A D | mediatek,mt8365-clk.h | 88 #define CLK_TOP_AUD_1_SEL 78 macro
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| H A D | mt6765-clk.h | 148 #define CLK_TOP_AUD_1_SEL 113 macro
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| H A D | mt8173-clk.h | 119 #define CLK_TOP_AUD_1_SEL 109 macro
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| H A D | mt2712-clk.h | 156 #define CLK_TOP_AUD_1_SEL 125 macro
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| H A D | mt8192-clk.h | 59 #define CLK_TOP_AUD_1_SEL 47 macro
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| /kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt6765-clk.h | 148 #define CLK_TOP_AUD_1_SEL 113 macro
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| H A D | mt8173-clk.h | 119 #define CLK_TOP_AUD_1_SEL 109 macro
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| H A D | mt2712-clk.h | 156 #define CLK_TOP_AUD_1_SEL 125 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| H A D | mt6765-clk.h | 148 #define CLK_TOP_AUD_1_SEL 113 macro
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| H A D | mt8173-clk.h | 119 #define CLK_TOP_AUD_1_SEL 109 macro
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| H A D | mt2712-clk.h | 156 #define CLK_TOP_AUD_1_SEL 125 macro
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 494 TOP_MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0xa0, 24, 2, 31, 0),
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| H A D | clk-mt8173-topckgen.c | 583 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
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| H A D | clk-mt2712.c | 686 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31),
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| H A D | clk-mt6765.c | 425 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
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| H A D | clk-mt8365.c | 456 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mt8173.c | 579 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
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| H A D | clk-mt2712.c | 796 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
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