| /kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 147 #define CLK_PERI_UART1 9 macro
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| H A D | mt8173-clk.h | 215 #define CLK_PERI_UART1 21 macro
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| H A D | mt2701-clk.h | 242 #define CLK_PERI_UART1 21 macro
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| H A D | mt2712-clk.h | 256 #define CLK_PERI_UART1 17 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 147 #define CLK_PERI_UART1 9 macro
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| H A D | mt8173-clk.h | 215 #define CLK_PERI_UART1 21 macro
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| H A D | mt2701-clk.h | 242 #define CLK_PERI_UART1 21 macro
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| H A D | mt2712-clk.h | 256 #define CLK_PERI_UART1 17 macro
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| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 195 #define CLK_PERI_UART1 20 macro
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| H A D | mt8135-clk.h | 147 #define CLK_PERI_UART1 9 macro
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| H A D | mt8173-clk.h | 214 #define CLK_PERI_UART1 21 macro
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| H A D | mt2701-clk.h | 242 #define CLK_PERI_UART1 21 macro
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| H A D | mt2712-clk.h | 256 #define CLK_PERI_UART1 17 macro
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mt8173-pericfg.c | 71 GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
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| H A D | clk-mt6795-pericfg.c | 60 GATE_PERI(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
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| H A D | clk-mt8135.c | 458 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
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| H A D | clk-mt2712.c | 902 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21),
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| H A D | clk-mt2701.c | 835 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
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| /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 195 #define CLK_PERI_UART1 20 macro
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| H A D | mt8135-clk.h | 147 #define CLK_PERI_UART1 9 macro
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| H A D | mt8173-clk.h | 214 #define CLK_PERI_UART1 21 macro
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| H A D | mt2701-clk.h | 242 #define CLK_PERI_UART1 21 macro
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| H A D | mt2712-clk.h | 256 #define CLK_PERI_UART1 17 macro
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mt8135.c | 468 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
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| H A D | clk-mt2701.c | 840 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
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