| /kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 148 #define CLK_PERI_UART0 10 macro
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| H A D | mt8173-clk.h | 214 #define CLK_PERI_UART0 20 macro
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| H A D | mt2701-clk.h | 241 #define CLK_PERI_UART0 20 macro
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| H A D | mt2712-clk.h | 255 #define CLK_PERI_UART0 16 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 148 #define CLK_PERI_UART0 10 macro
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| H A D | mt8173-clk.h | 214 #define CLK_PERI_UART0 20 macro
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| H A D | mt2701-clk.h | 241 #define CLK_PERI_UART0 20 macro
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| H A D | mt2712-clk.h | 255 #define CLK_PERI_UART0 16 macro
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| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 194 #define CLK_PERI_UART0 19 macro
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| H A D | mt8135-clk.h | 148 #define CLK_PERI_UART0 10 macro
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| H A D | mt8173-clk.h | 213 #define CLK_PERI_UART0 20 macro
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| H A D | mt2701-clk.h | 241 #define CLK_PERI_UART0 20 macro
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| H A D | mt2712-clk.h | 255 #define CLK_PERI_UART0 16 macro
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mt8173-pericfg.c | 70 GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
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| H A D | clk-mt6795-pericfg.c | 59 GATE_PERI(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
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| H A D | clk-mt8135.c | 459 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
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| H A D | clk-mt2712.c | 901 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
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| H A D | clk-mt2701.c | 836 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
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| /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 194 #define CLK_PERI_UART0 19 macro
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| H A D | mt8135-clk.h | 148 #define CLK_PERI_UART0 10 macro
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| H A D | mt8173-clk.h | 213 #define CLK_PERI_UART0 20 macro
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| H A D | mt2701-clk.h | 241 #define CLK_PERI_UART0 20 macro
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| H A D | mt2712-clk.h | 255 #define CLK_PERI_UART0 16 macro
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mt8135.c | 469 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
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| H A D | clk-mt2701.c | 841 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
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