| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | rv740d.h | 34 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | rv730d.h | 37 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | rv740_dpm.c | 295 RREG32(CG_SPLL_FUNC_CNTL_2); in rv740_read_clock_registers()
|
| H A D | rv730_dpm.c | 204 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
|
| H A D | rv770.c | 1145 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_set_clk_bypass_mode()
1148 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
1157 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
|
| H A D | rv770d.h | 100 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | nid.h | 547 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | si.c | 3999 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4001 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4009 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4011 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
|
| H A D | cikd.h | 257 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 macro
|
| H A D | sid.h | 94 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | rv740d.h | 34 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | rv730d.h | 37 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | rv740_dpm.c | 294 RREG32(CG_SPLL_FUNC_CNTL_2); in rv740_read_clock_registers()
|
| H A D | rv730_dpm.c | 202 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
|
| H A D | rv770.c | 1142 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in rv770_set_clk_bypass_mode()
1145 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
1154 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
|
| H A D | rv770d.h | 100 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | nid.h | 547 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| H A D | si.c | 3994 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
3996 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4004 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
4006 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
|
| H A D | cikd.h | 257 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 macro
|
| H A D | sid.h | 94 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si.c | 1228 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
1230 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
1238 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
1240 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
|
| H A D | sid.h | 95 #define CG_SPLL_FUNC_CNTL_2 0x181 macro
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si.c | 1338 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
1340 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
1348 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); in si_set_clk_bypass_mode()
1350 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
|
| H A D | sid.h | 95 #define CG_SPLL_FUNC_CNTL_2 0x181 macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | fiji_smumgr.c | 1348 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, in fiji_populate_smc_acpi_level()
|