Searched refs:CCR2 (Results 1 - 9 of 9) sorted by relevance
| /kernel/linux/linux-5.10/arch/arm/plat-omap/ |
| H A D | dma.c | 190 ccr = p->dma_read(CCR2, lch); in omap_set_dma_transfer_params()
194 p->dma_write(ccr, CCR2, lch); in omap_set_dma_transfer_params()
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| /kernel/linux/linux-6.6/arch/arm/mach-omap1/ |
| H A D | omap-dma.c | 164 ccr = p->dma_read(CCR2, lch); in omap_set_dma_transfer_params()
168 p->dma_write(ccr, CCR2, lch); in omap_set_dma_transfer_params()
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| H A D | dma.c | 75 [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
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| /kernel/linux/linux-5.10/drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 270 #define CCR2 0x2e macro
2890 * BGR[9..8] contained in CCR2[7..6] in mgslpc_set_rate()
2897 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; in mgslpc_set_rate()
2899 write_reg(info, (unsigned char) (channel + CCR2), val); in mgslpc_set_rate()
2953 /* CCR2 (Channel B) in enable_auxclk()
2966 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
2968 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
3000 /* CCR2:04 SSEL Clock source select, 1=submode b */ in loopback_enable()
3001 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3002 write_reg(info, CHA + CCR2, va in loopback_enable()
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| /kernel/linux/linux-5.10/arch/arm/mach-omap1/ |
| H A D | dma.c | 75 [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
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| /kernel/linux/linux-5.10/include/linux/ |
| H A D | omap-dma.h | 150 CPC, CCR2, LCH_CTRL, enumerator
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| /kernel/linux/linux-6.6/include/linux/ |
| H A D | omap-dma.h | 150 CPC, CCR2, LCH_CTRL, enumerator
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| /kernel/linux/linux-5.10/drivers/dma/ti/ |
| H A D | omap-dma.c | 589 omap_dma_chan_write(c, CCR2, d->ccr >> 16); in omap_dma_start_desc()
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| /kernel/linux/linux-6.6/drivers/dma/ti/ |
| H A D | omap-dma.c | 589 omap_dma_chan_write(c, CCR2, d->ccr >> 16); in omap_dma_start_desc()
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