BANK_WIDTH (reference) in projects: kernel

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Searched refs:BANK_WIDTH (Results 1 - 25 of 30) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v6_0.c	84 #define BANK_WIDTH(x) ((x) << 14) macro 423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 439 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 458 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 466 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 474 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 486 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 494 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in gfx_v6_0_tiling_mode_table_init() [all...]
H A D	gfx_v8_0.c	72 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) macro 2229 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) \| in gfx_v8_0_tiling_mode_table_init() 2233 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) \| in gfx_v8_0_tiling_mode_table_init() 2237 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \| in gfx_v8_0_tiling_mode_table_init() 2241 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2245 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2249 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2253 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2257 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) \| in gfx_v8_0_tiling_mode_table_init() 2261 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in gfx_v8_0_tiling_mode_table_init() [all...]
H A D	gfx_v7_0.c	1158 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1162 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1166 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1170 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1174 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1178 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1182 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1186 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \| in gfx_v7_0_tiling_mode_table_init() 1190 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \| in gfx_v7_0_tiling_mode_table_init() 1194 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in gfx_v7_0_tiling_mode_table_init() [all...]
H A D	cikd.h	`194 # define BANK_WIDTH(x) ((x) << 0) macro`
H A D	sid.h	`1203 # define BANK_WIDTH(x) ((x) << 14) macro`
H A D	dce_v11_0.c	`2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()`
H A D	dce_v8_0.c	`1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()`
H A D	dce_v10_0.c	`1991 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()`
H A D	dce_v6_0.c	`1940 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v6_0.c	84 #define BANK_WIDTH(x) ((x) << 14) macro 409 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 417 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 425 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 452 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 460 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v6_0_tiling_mode_table_init() 480 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in gfx_v6_0_tiling_mode_table_init() [all...]
H A D	gfx_v8_0.c	73 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) macro 2195 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) \| in gfx_v8_0_tiling_mode_table_init() 2199 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) \| in gfx_v8_0_tiling_mode_table_init() 2203 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \| in gfx_v8_0_tiling_mode_table_init() 2207 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2211 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2215 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2219 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v8_0_tiling_mode_table_init() 2223 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) \| in gfx_v8_0_tiling_mode_table_init() 2227 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in gfx_v8_0_tiling_mode_table_init() [all...]
H A D	gfx_v7_0.c	1122 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1126 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1130 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1134 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1138 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1142 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1146 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in gfx_v7_0_tiling_mode_table_init() 1150 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \| in gfx_v7_0_tiling_mode_table_init() 1154 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \| in gfx_v7_0_tiling_mode_table_init() 1158 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in gfx_v7_0_tiling_mode_table_init() [all...]
H A D	cikd.h	`194 # define BANK_WIDTH(x) ((x) << 0) macro`
H A D	sid.h	`1203 # define BANK_WIDTH(x) ((x) << 14) macro`
H A D	dce_v8_0.c	`1910 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()`
H A D	dce_v11_0.c	`2035 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()`
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	si.c	2525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2543 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2552 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2561 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2579 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2588 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2597 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2606 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in si_tiling_mode_table_init() [all...]
H A D	cik.c	2445 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2449 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2453 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2457 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2461 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2465 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2469 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2473 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2477 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2481 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in cik_tiling_mode_table_init() [all...]
H A D	cikd.h	`1260 # define BANK_WIDTH(x) ((x) << 0) macro`
H A D	sid.h	`1206 # define BANK_WIDTH(x) ((x) << 14) macro`
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	si.c	2520 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2556 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in si_tiling_mode_table_init() 2601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in si_tiling_mode_table_init() [all...]
H A D	cik.c	2436 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2440 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2444 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2448 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2452 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2456 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2460 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2464 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2468 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \| in cik_tiling_mode_table_init() 2472 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_ in cik_tiling_mode_table_init() [all...]
H A D	cikd.h	`1260 # define BANK_WIDTH(x) ((x) << 0) macro`
H A D	sid.h	`1206 # define BANK_WIDTH(x) ((x) << 14) macro`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/amdgpu_dm/
H A D	amdgpu_dm_plane.c	`187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_gfx8_tiling_info_from_flags()`

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