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Searched refs:AVIVO_D1GRPH_UPDATE (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drs600.c121 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
126 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
138 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
146 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
154 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
H A Drv515.c366 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_stop()
369 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_stop()
416 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
419 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_resume()
427 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
H A Drv770.c811 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
816 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
835 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
843 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
851 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
H A Dr500_reg.h419 #define AVIVO_D1GRPH_UPDATE 0x6144 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drs600.c124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
129 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
153 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
H A Drv515.c336 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_stop()
339 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_stop()
386 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
389 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_resume()
397 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
H A Drv770.c804 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
832 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
840 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
848 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
H A Dr500_reg.h419 #define AVIVO_D1GRPH_UPDATE 0x6144 macro

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