AR71XX_RESET_REG_MISC_INT_ENABLE (reference) in projects: kernel - OpenGrok search results

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Searched refs:AR71XX_RESET_REG_MISC_INT_ENABLE (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/irqchip/
H A D	irq-ath79-misc.c	19 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4 macro 42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler() 66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 67 __raw_writel(t \| BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() 80 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() local 83 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() 125 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_intc_domain_init()
/kernel/linux/linux-6.6/drivers/irqchip/
H A D	irq-ath79-misc.c	19 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4 macro 42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler() 66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 67 __raw_writel(t \| BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() 80 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() local 83 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() 125 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_intc_domain_init()
/kernel/linux/linux-5.10/arch/mips/ath79/
H A D	clock.c	`532 misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); in qca956x_clocks_init() 534 ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); in qca956x_clocks_init()`
/kernel/linux/linux-6.6/arch/mips/ath79/
H A D	clock.c	`532 misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); in qca956x_clocks_init() 534 ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); in qca956x_clocks_init()`
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-ath79/
H A D	ar71xx_regs.h	`517 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 macro`
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-ath79/
H A D	ar71xx_regs.h	`517 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 macro`

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