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Searched refs:ADDR_MASK (Results 1 - 20 of 20) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/microchip/
H A Dencx24j600_hw.h66 #define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */
67 #define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */
70 #define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */
71 #define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */
89 #define ADDR_MASK 0x1F macro
H A Dencx24j600-regmap.c64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
H A Denc28j60_hw.h19 #define ADDR_MASK 0x1F macro
H A Denc28j60.c156 tx_buf[0] = op | (addr & ADDR_MASK); in spi_read_op()
175 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); in spi_write_op()
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/
H A Dencx24j600_hw.h66 #define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */
67 #define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */
70 #define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */
71 #define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */
89 #define ADDR_MASK 0x1F macro
H A Dencx24j600-regmap.c64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
H A Denc28j60_hw.h19 #define ADDR_MASK 0x1F macro
H A Denc28j60.c155 tx_buf[0] = op | (addr & ADDR_MASK); in spi_read_op()
174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); in spi_write_op()
/kernel/linux/linux-5.10/arch/h8300/kernel/
H A Dirq.c34 base = rom_vector[EXT_IRQ0] & ADDR_MASK; in get_vector_address()
39 (rom_vector[vec_no] & ADDR_MASK)) in get_vector_address()
/kernel/linux/linux-5.10/arch/h8300/include/asm/
H A Dtraps.h27 #define ADDR_MASK (0xffffff) macro
/kernel/linux/linux-5.10/arch/mips/kernel/
H A Dftrace.c41 #define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ macro
46 ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK)))
/kernel/linux/linux-6.6/arch/mips/kernel/
H A Dftrace.c41 #define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ macro
46 ((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK)))
/kernel/linux/linux-5.10/drivers/macintosh/
H A Dadb-iop.c47 #define ADDR_MASK 0xF0 macro
104 u8 addr = (amsg->cmd & ADDR_MASK) >> 4; in adb_iop_listen()
H A Dvia-macii.c81 #define ADDR_MASK 0xF0 macro
205 poll_addr = (last_poll_cmd & ADDR_MASK) >> 4; in macii_queue_poll()
/kernel/linux/linux-6.6/drivers/macintosh/
H A Dadb-iop.c47 #define ADDR_MASK 0xF0 macro
104 u8 addr = (amsg->cmd & ADDR_MASK) >> 4; in adb_iop_listen()
H A Dvia-macii.c79 #define ADDR_MASK 0xF0 macro
203 poll_addr = (last_poll_cmd & ADDR_MASK) >> 4; in macii_queue_poll()
/kernel/linux/linux-5.10/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_main.c326 adrmask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()
327 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()
329 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()
334 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()
336 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()
388 iowrite32(0xFFFE, &hw->reg->ADDR_MASK); in pch_gbe_mac_init_rx_addrs()
390 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_init_rx_addrs()
451 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n", in pch_gbe_mac_set_wol_event()
452 wu_evt, ioread32(&hw->reg->ADDR_MASK)); in pch_gbe_mac_set_wol_event()
456 addr_mask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_set_wol_event()
[all...]
H A Dpch_gbe.h62 u32 ADDR_MASK; member
/kernel/linux/linux-6.6/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_main.c318 adrmask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()
319 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()
321 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()
326 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); in pch_gbe_mac_mar_set()
328 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_mar_set()
380 iowrite32(0xFFFE, &hw->reg->ADDR_MASK); in pch_gbe_mac_init_rx_addrs()
382 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); in pch_gbe_mac_init_rx_addrs()
443 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n", in pch_gbe_mac_set_wol_event()
444 wu_evt, ioread32(&hw->reg->ADDR_MASK)); in pch_gbe_mac_set_wol_event()
448 addr_mask = ioread32(&hw->reg->ADDR_MASK); in pch_gbe_mac_set_wol_event()
[all...]
H A Dpch_gbe.h62 u32 ADDR_MASK; member

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