Searched refs:xvclk (Results 1 - 2 of 2) sorted by relevance
| /device/soc/rockchip/common/vendor/drivers/media/i2c/ |
| H A D | gc2093.c | 131 struct clk *xvclk;
member
681 ret = clk_set_rate(gc2093->xvclk, GC2093_XVCLK_FREQ);
in __gc2093_power_on()
683 dev_warn(dev, "Failed to set xvclk rate\n");
in __gc2093_power_on()
686 if (clk_get_rate(gc2093->xvclk) != GC2093_XVCLK_FREQ) {
in __gc2093_power_on()
687 dev_warn(dev, "xvclk mismatched, modes are based on 27MHz\n");
in __gc2093_power_on()
690 ret = clk_prepare_enable(gc2093->xvclk);
in __gc2093_power_on()
692 dev_err(dev, "Failed to enable xvclk\n");
in __gc2093_power_on()
720 clk_disable_unprepare(gc2093->xvclk);
in __gc2093_power_on()
734 clk_disable_unprepare(gc2093->xvclk);
in __gc2093_power_off()
1322 gc2093->xvclk in gc2093_probe()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/media/i2c/ |
| H A D | ov13855.c | 116 struct clk *xvclk; member
1541 ret = clk_set_rate(ov13855->xvclk, OV13855_XVCLK_FREQ); in __ov13855_power_on()
1543 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); in __ov13855_power_on()
1544 if (clk_get_rate(ov13855->xvclk) != OV13855_XVCLK_FREQ) in __ov13855_power_on()
1545 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); in __ov13855_power_on()
1546 ret = clk_prepare_enable(ov13855->xvclk); in __ov13855_power_on()
1548 dev_err(dev, "Failed to enable xvclk\n"); in __ov13855_power_on()
1574 clk_disable_unprepare(ov13855->xvclk); in __ov13855_power_on()
1586 clk_disable_unprepare(ov13855->xvclk); in __ov13855_power_off()
1951 ov13855->xvclk in ov13855_probe()
[all...] |
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