| /device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/ |
| H A D | flash.h | 83 writel(0x1a3, IO_MUX_REG_BASE + 0x91c); in nand_io_config()
84 writel(0x103, IO_MUX_REG_BASE + 0x920); in nand_io_config()
85 writel(0x100, IO_MUX_REG_BASE + 0x924); in nand_io_config()
86 writel(0x1a3, IO_MUX_REG_BASE + 0x928); in nand_io_config()
87 writel(0x100, IO_MUX_REG_BASE + 0x92c); in nand_io_config()
88 writel(0x100, IO_MUX_REG_BASE + 0x930); in nand_io_config()
93 writel(reg_val, MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
98 writel(reg_val, EMMC_PHY_INIT_CTRL); in nand_io_config()
113 writel((RG_EMMC_RONSEL1 << 16) | RG_EMMC_RONSEL0, in nand_io_config()
116 writel( in nand_io_config()
[all...] |
| /device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/ |
| H A D | flash.h | 83 writel(0x1a3, IO_MUX_REG_BASE + 0x91c); in nand_io_config()
84 writel(0x103, IO_MUX_REG_BASE + 0x920); in nand_io_config()
85 writel(0x100, IO_MUX_REG_BASE + 0x924); in nand_io_config()
86 writel(0x1a3, IO_MUX_REG_BASE + 0x928); in nand_io_config()
87 writel(0x100, IO_MUX_REG_BASE + 0x92c); in nand_io_config()
88 writel(0x100, IO_MUX_REG_BASE + 0x930); in nand_io_config()
93 writel(reg_val, MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
98 writel(reg_val, EMMC_PHY_INIT_CTRL); in nand_io_config()
113 writel((RG_EMMC_RONSEL1 << 16) | RG_EMMC_RONSEL0, in nand_io_config()
116 writel( in nand_io_config()
[all...] |
| /device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/ |
| H A D | lowlevel_init_v300.c | 46 static inline void writel(unsigned val, unsigned addr) in writel() function
83 #define reg_set(addr, val) writel(val, (unsigned int)addr)
200 writel(sysboot10.u32, HPM_CHECK_REG); in hpm_check()
253 writel(volt, SYS_CTRL_VOLT_REG); in set_hpm_core_volt()
255 writel(duty, PWM0_REG + pwm_id * PWM_REG_OFFSET + PWM_CFG1); in set_hpm_core_volt()
256 writel(0x5, PWM0_REG + pwm_id * PWM_REG_OFFSET + PWM_CTRL); in set_hpm_core_volt()
267 writel(tmp_reg, SVB_VER_REG); in start_svb()
315 writel(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4); in ddr_boot_prepare()
320 writel(reg->custom.ddrt_clk_reg | (0x1 << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_prepare()
323 writel(read in ddr_boot_prepare()
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/nvmem/ |
| H A D | rockchip-efuse.c | 108 writel(readl(base + RK1808_MOD) & (~RK1808_USER_MODE), base + RK1808_MOD);
in rk1808_efuse_timing_init()
111 writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
in rk1808_efuse_timing_init()
112 writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
in rk1808_efuse_timing_init()
113 writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
in rk1808_efuse_timing_init()
114 writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
in rk1808_efuse_timing_init()
115 writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
in rk1808_efuse_timing_init()
116 writel((T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
in rk1808_efuse_timing_init()
117 writel((T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
in rk1808_efuse_timing_init()
118 writel((T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
in rk1808_efuse_timing_init()
119 writel((T_ADDR_R_ in rk1808_efuse_timing_init()
[all...] |
| H A D | rockchip-otp.c | 111 writel(flag, otp->base + OTPC_INT_STATUS);
in rockchip_otp_wait_status()
120 writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT), otp->base + OTPC_SBPI_CTRL);
in rockchip_otp_ecc_enable()
122 writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE);
in rockchip_otp_ecc_enable()
123 writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC, otp->base + OTPC_SBPI_CMD0_OFFSET);
in rockchip_otp_ecc_enable()
125 writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
in rockchip_otp_ecc_enable()
127 writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
in rockchip_otp_ecc_enable()
130 writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
in rockchip_otp_ecc_enable()
164 writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
in rockchip_otp_read()
167 writel(offset++ | OTPC_USER_ADDR_MASK, otp->base + OTPC_USER_ADDR);
in rockchip_otp_read()
168 writel(OTPC_USER_FSM_ENABL in rockchip_otp_read()
[all...] |
| /device/soc/rockchip/common/vendor/drivers/phy/ |
| H A D | phy-rockchip-naneng-edp.c | 92 writel(EDP_PHY_TX_AMP(lane, val), edpphy->regs + EDP_PHY_GRF_CON4);
in rockchip_edp_phy_set_voltages()
95 writel(EDP_PHY_TX_AMP_SCALE(lane, val), edpphy->regs + EDP_PHY_GRF_CON5);
in rockchip_edp_phy_set_voltages()
98 writel(EDP_PHY_TX_EMP(lane, val), edpphy->regs + EDP_PHY_GRF_CON3);
in rockchip_edp_phy_set_voltages()
109 writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf), edpphy->regs + EDP_PHY_GRF_CON0);
in rockchip_edp_phy_set_rate()
111 writel(EDP_PHY_TX_MODE(0x3), edpphy->regs + EDP_PHY_GRF_CON5);
in rockchip_edp_phy_set_rate()
112 writel(EDP_PHY_PD_PLL(0x1), edpphy->regs + EDP_PHY_GRF_CON0);
in rockchip_edp_phy_set_rate()
116 writel(EDP_PHY_PLL_DIV(0x4380), edpphy->regs + EDP_PHY_GRF_CON1);
in rockchip_edp_phy_set_rate()
117 writel(EDP_PHY_TX_RTERM(0x1) | EDP_PHY_RATE(0x1) | EDP_PHY_REF_DIV(0x0), edpphy->regs + EDP_PHY_GRF_CON2);
in rockchip_edp_phy_set_rate()
118 writel(EDP_PHY_PLL_CTL_H(0x0800), edpphy->regs + EDP_PHY_GRF_CON8);
in rockchip_edp_phy_set_rate()
119 writel(EDP_PHY_TX_CT in rockchip_edp_phy_set_rate()
[all...] |
| H A D | phy-rockchip-naneng-combphy.c | 146 writel(val, priv->mmio + (0x19 << 0x02));
in rockchip_combphy_pcie_init()
441 writel(val, priv->mmio + 0x7c);
in rk3568_combphy_cfg()
453 writel(val, priv->mmio + 0x7c);
in rk3568_combphy_cfg()
459 writel(val, priv->mmio + (0x0e << 0x02));
in rk3568_combphy_cfg()
465 writel(val, priv->mmio + (0x20 << 0x02));
in rk3568_combphy_cfg()
468 writel(0x4, priv->mmio + (0xb << 0x02));
in rk3568_combphy_cfg()
474 writel(val, priv->mmio + (0x5 << 0x02));
in rk3568_combphy_cfg()
477 writel(0x32, priv->mmio + (0x11 << 0x02));
in rk3568_combphy_cfg()
480 writel(0xf0, priv->mmio + (0xa << 0x02));
in rk3568_combphy_cfg()
488 writel( in rk3568_combphy_cfg()
[all...] |
| H A D | phy-rockchip-inno-usb3.c | 246 writel(0x30, u3phy_port->base + 0xd8);
in rockchip_u3phy_usb2_only_write()
265 writel(0x20, u3phy_port->base + 0xd8);
in rockchip_u3phy_usb2_only_write()
940 writel(reg, u3phy_port->base + 0x1a8);
in rk3328_u3phy_pipe_power()
944 writel(reg, u3phy_port->base + 0x044);
in rk3328_u3phy_pipe_power()
948 writel(reg, u3phy_port->base + 0x150);
in rk3328_u3phy_pipe_power()
952 writel(reg, u3phy_port->base + 0x080);
in rk3328_u3phy_pipe_power()
957 writel(reg, u3phy_port->base + 0x0c0);
in rk3328_u3phy_pipe_power()
963 writel(reg, u3phy_port->base + 0x1a8);
in rk3328_u3phy_pipe_power()
967 writel(reg, u3phy_port->base + 0x044);
in rk3328_u3phy_pipe_power()
971 writel(re in rk3328_u3phy_pipe_power()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-naneng-edp.c | 97 writel(EDP_PHY_TX_AMP(lane, val), in rockchip_edp_phy_set_voltages()
101 writel(EDP_PHY_TX_AMP_SCALE(lane, val), in rockchip_edp_phy_set_voltages()
105 writel(EDP_PHY_TX_EMP(lane, val), in rockchip_edp_phy_set_voltages()
118 writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf), in rockchip_edp_phy_set_rate()
121 writel(EDP_PHY_TX_MODE(0x3), edpphy->regs + EDP_PHY_GRF_CON5); in rockchip_edp_phy_set_rate()
122 writel(EDP_PHY_PD_PLL(0x1), edpphy->regs + EDP_PHY_GRF_CON0); in rockchip_edp_phy_set_rate()
126 writel(EDP_PHY_PLL_DIV(0x4380), in rockchip_edp_phy_set_rate()
128 writel(EDP_PHY_TX_RTERM(0x1) | EDP_PHY_RATE(0x1) | in rockchip_edp_phy_set_rate()
130 writel(EDP_PHY_PLL_CTL_H(0x0800), in rockchip_edp_phy_set_rate()
132 writel(EDP_PHY_TX_CT in rockchip_edp_phy_set_rate()
[all...] |
| H A D | phy-rockchip-naneng-combphy.c | 148 writel(val, priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
446 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
458 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
464 writel(val, priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
470 writel(val, priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
473 writel(0x4, priv->mmio + (0xb << 2)); in rk3568_combphy_cfg()
479 writel(val, priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
482 writel(0x32, priv->mmio + (0x11 << 2)); in rk3568_combphy_cfg()
485 writel(0xf0, priv->mmio + (0xa << 2)); in rk3568_combphy_cfg()
493 writel( in rk3568_combphy_cfg()
[all...] |
| H A D | phy-rockchip-inno-usb3.c | 254 writel(0x30, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
276 writel(0x20, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
968 writel(reg, u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
972 writel(reg, u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
976 writel(reg, u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
980 writel(reg, u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
985 writel(reg, u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
991 writel(reg, u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
995 writel(reg, u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
999 writel(re in rk3328_u3phy_pipe_power()
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-typec.c | 565 writel(reg, tcphy->base + PHY_DP_MODE_CTL);
in tcphy_dp_set_power_state()
626 writel(PMA_LANE3_DP_LANE_SEL(PHY_DP_LANE_1) | PMA_LANE3_INTERFACE_SEL(PMA_IF_PHY_DP) |
in tcphy_set_lane_mapping()
633 writel(PMA_LANE3_DP_LANE_SEL(PHY_DP_LANE_1) | PMA_LANE3_INTERFACE_SEL(PMA_IF_PHY_DP) |
in tcphy_set_lane_mapping()
648 writel(0x830, tcphy->base + PMA_CMN_CTRL1);
in tcphy_cfg_24m()
654 writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
in tcphy_cfg_24m()
655 writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i));
in tcphy_cfg_24m()
656 writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i));
in tcphy_cfg_24m()
662 writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL);
in tcphy_cfg_24m()
671 writel(usb3_pll_cfg[i].value, tcphy->base + usb3_pll_cfg[i].addr);
in tcphy_cfg_usb3_pll()
707 writel(clk_ctr in tcphy_cfg_dp_pll()
[all...] |
| /device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/ispp/ |
| H A D | hw.c | 43 writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
45 writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
59 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL); in rkispp_soft_reset()
60 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL); in rkispp_soft_reset()
61 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL); in rkispp_soft_reset()
62 writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE); in rkispp_soft_reset()
63 writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE); in rkispp_soft_reset()
64 writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL); in rkispp_soft_reset()
65 writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR | FBCH_EMPTY_TNR | FBCD_DEC_ERR_NR | FBCD_DEC_ERR_TNR | in rkispp_soft_reset()
69 writel(GATE_DIS_N in rkispp_soft_reset()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/ispp/ |
| H A D | hw.c | 44 writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
46 writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
60 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL); in rkispp_soft_reset()
61 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL); in rkispp_soft_reset()
62 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL); in rkispp_soft_reset()
63 writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE); in rkispp_soft_reset()
64 writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE); in rkispp_soft_reset()
65 writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL); in rkispp_soft_reset()
66 writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR | in rkispp_soft_reset()
71 writel(GATE_DIS_N in rkispp_soft_reset()
[all...] |
| /device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/hack/ |
| H A D | mpp_hack_px30.c | 71 writel(RK_MMU_CMD_ENABLE_STALL, iommu->bases[i] + RK_MMU_COMMAND);
in mpp_iommu_enable()
76 writel(RK_MMU_CMD_FORCE_RESET, iommu->bases[i] + RK_MMU_COMMAND);
in mpp_iommu_enable()
82 writel(iommu->dte_addr, iommu->bases[i] + RK_MMU_DTE_ADDR);
in mpp_iommu_enable()
84 writel(RK_MMU_CMD_ZAP_CACHE, iommu->bases[i] + RK_MMU_COMMAND);
in mpp_iommu_enable()
86 writel(RK_MMU_IRQ_MASK, iommu->bases[i] + RK_MMU_INT_MASK);
in mpp_iommu_enable()
91 writel(RK_MMU_CMD_ENABLE_PAGING, iommu->bases[i] + RK_MMU_COMMAND);
in mpp_iommu_enable()
96 writel(RK_MMU_CMD_DISABLE_STALL, iommu->bases[i] + RK_MMU_COMMAND);
in mpp_iommu_enable()
121 writel(RK_MMU_CMD_ENABLE_STALL, iommu->bases[i] + RK_MMU_COMMAND);
in mpp_iommu_disable()
126 writel(RK_MMU_CMD_DISABLE_PAGING, iommu->bases[i] + RK_MMU_COMMAND);
in mpp_iommu_disable()
131 writel(RK_MMU_CMD_DISABLE_STAL in mpp_iommu_disable()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/hack/ |
| H A D | mpp_hack_px30.c | 73 writel(RK_MMU_CMD_ENABLE_STALL, in mpp_iommu_enable()
78 writel(RK_MMU_CMD_FORCE_RESET, in mpp_iommu_enable()
84 writel(iommu->dte_addr, in mpp_iommu_enable()
87 writel(RK_MMU_CMD_ZAP_CACHE, in mpp_iommu_enable()
90 writel(RK_MMU_IRQ_MASK, in mpp_iommu_enable()
96 writel(RK_MMU_CMD_ENABLE_PAGING, in mpp_iommu_enable()
101 writel(RK_MMU_CMD_DISABLE_STALL, in mpp_iommu_enable()
128 writel(RK_MMU_CMD_ENABLE_STALL, in mpp_iommu_disable()
133 writel(RK_MMU_CMD_DISABLE_PAGING, in mpp_iommu_disable()
138 writel(RK_MMU_CMD_DISABLE_STAL in mpp_iommu_disable()
[all...] |
| /device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/ |
| H A D | lowlevel_init_v300.c | 46 static inline void writel(unsigned val, unsigned addr) in writel() function
83 #define reg_set(addr, val) writel(val, (unsigned int)addr)
312 writel(sysboot10.u32, HPM_CHECK_REG); in hpm_check()
377 writel((unsigned int)svb_value, HI_PMC_CTL_REG); in set_hpm_core_volt()
429 writel(tmp_reg, SVB_VER_REG); in start_svb()
471 writel(0x401, DDR_REG_BASE_DMC0 + 0x28); in start_ddr_training()
472 writel(0x401, DDR_REG_BASE_DMC1 + 0x28); in start_ddr_training()
474 writel(0x401, DDR_REG_BASE_DMC0 + 0x28); in start_ddr_training()
479 writel(0x401, DDR_REG_BASE_DMC2 + 0x28); in start_ddr_training()
480 writel( in start_ddr_training()
[all...] |
| /device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/ |
| H A D | regs.h | 1616 writel(reg | burst, addr);
in config_mi_ctrl()
1618 writel(reg | CIF_MI_CTRL_INIT_BASE_EN, addr);
in config_mi_ctrl()
1620 writel(reg | CIF_MI_CTRL_INIT_OFFSET_EN, addr);
in config_mi_ctrl()
1640 writel(tmp | val, addr);
in isp_set_bits()
1647 writel(val & ~bit_mask, addr);
in isp_clear_bits()
1654 writel(val, base + stream->config->mi.y_size_init);
in mi_set_y_size()
1661 writel(val, base + stream->config->mi.cb_size_init);
in mi_set_cb_size()
1668 writel(val, base + stream->config->mi.cr_size_init);
in mi_set_cr_size()
1675 writel(val, base + stream->config->mi.y_base_ad_init);
in mi_set_y_addr()
1682 writel(va in mi_set_cb_addr()
[all...] |
| H A D | rkisp.c | 555 writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
in rkisp_trigger_read_back()
561 writel(val, hw->base_addr + MI_WR_CTRL2);
in rkisp_trigger_read_back()
565 writel(val, hw->base_addr + ISP3X_MPFBC_CTRL);
in rkisp_trigger_read_back()
570 writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
in rkisp_trigger_read_back()
915 writel(*reg1, base + backup[i].base);
in rkisp_reset_handle_v2x()
927 writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
in rkisp_reset_handle_v2x()
931 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
in rkisp_reset_handle_v2x()
935 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
in rkisp_reset_handle_v2x()
942 writel(*reg, base + ISP_CTRL);
in rkisp_reset_handle_v2x()
946 writel(backu in rkisp_reset_handle_v2x()
[all...] |
| H A D | hw.c | 657 writel(0xffff, base + CIF_IRCL); in rkisp_soft_reset()
659 writel(0xffff, dev->base_next_addr + CIF_IRCL); in rkisp_soft_reset()
673 writel(CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601, base + CIF_ISP_CTRL); in rkisp_soft_reset()
675 writel(0xffff, base + CIF_IRCL); in rkisp_soft_reset()
677 writel(0xffff, dev->base_next_addr + CIF_IRCL); in rkisp_soft_reset()
698 writel(val, dev->base_addr + CIF_ICCL); in isp_config_clk()
700 writel(val, dev->base_next_addr + CIF_ICCL); in isp_config_clk()
708 writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12); in isp_config_clk()
718 writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL); in isp_config_clk()
720 writel(va in isp_config_clk()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/ |
| H A D | regs.h | 1639 writel(reg | burst, addr); in config_mi_ctrl()
1641 writel(reg | CIF_MI_CTRL_INIT_BASE_EN, addr); in config_mi_ctrl()
1643 writel(reg | CIF_MI_CTRL_INIT_OFFSET_EN, addr); in config_mi_ctrl()
1663 writel(tmp | val, addr); in isp_set_bits()
1670 writel(val & ~bit_mask, addr); in isp_clear_bits()
1677 writel(val, base + stream->config->mi.y_size_init); in mi_set_y_size()
1684 writel(val, base + stream->config->mi.cb_size_init); in mi_set_cb_size()
1691 writel(val, base + stream->config->mi.cr_size_init); in mi_set_cr_size()
1698 writel(val, base + stream->config->mi.y_base_ad_init); in mi_set_y_addr()
1705 writel(va in mi_set_cb_addr()
[all...] |
| H A D | rkisp.c | 584 writel(val, hw->base_addr + ISP_ACQ_H_OFFS); in rkisp_trigger_read_back()
592 writel(val, hw->base_addr + MI_WR_CTRL2); in rkisp_trigger_read_back()
596 writel(val, hw->base_addr + ISP3X_MPFBC_CTRL); in rkisp_trigger_read_back()
602 writel(val, hw->base_addr + ISP_ACQ_H_OFFS); in rkisp_trigger_read_back()
915 writel(*reg1, base + backup[i].base); in rkisp_reset_handle_v2x()
927 writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL); in rkisp_reset_handle_v2x()
930 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL); in rkisp_reset_handle_v2x()
933 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL); in rkisp_reset_handle_v2x()
941 writel(*reg, base + ISP_CTRL); in rkisp_reset_handle_v2x()
945 writel(backu in rkisp_reset_handle_v2x()
[all...] |
| H A D | hw.c | 650 writel(0xffff, base + CIF_IRCL); in rkisp_soft_reset()
652 writel(0xffff, dev->base_next_addr + CIF_IRCL); in rkisp_soft_reset()
665 writel(CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601, base + CIF_ISP_CTRL); in rkisp_soft_reset()
666 writel(0xffff, base + CIF_IRCL); in rkisp_soft_reset()
668 writel(0xffff, dev->base_next_addr + CIF_IRCL); in rkisp_soft_reset()
688 writel(val, dev->base_addr + CIF_ICCL); in isp_config_clk()
690 writel(val, dev->base_next_addr + CIF_ICCL); in isp_config_clk()
699 writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12); in isp_config_clk()
713 writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL); in isp_config_clk()
715 writel(va in isp_config_clk()
[all...] |
| /device/soc/hisilicon/common/platform/wifi/hi3881v100/adapter/ |
| H A D | hdf_wlan_sdio_adapt.c | 64 writel(VALUE, reg); \
76 writel(readl(reg) | (VALUE), reg); \
84 writel(VALUE, reg); \
91 writel(readl(reg) | (VALUE), reg); \
|
| /device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/cif/ |
| H A D | hw.h | 27 #define write_cif_reg(base, addr, val) writel(val, (addr) + (base))
29 #define write_cif_reg_or(base, addr, val) writel(readl((addr) + (base)) | (val), (addr) + (base))
30 #define write_cif_reg_and(base, addr, val) writel(readl((addr) + (base)) & (val), (addr) + (base))
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