Home
last modified time | relevance | path

Searched refs:ul (Results 1 - 25 of 55) sorted by relevance

123

/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_kbase_mem.h95 #define KBASE_MEM_PHY_ALLOC_ACCESSED_CACHED (1ul << 0)
96 #define KBASE_MEM_PHY_ALLOC_LARGE (1ul << 1)
227 #define KBASE_REG_FREE (1ul << 0)
229 #define KBASE_REG_CPU_WR (1ul << 1)
231 #define KBASE_REG_GPU_WR (1ul << 2)
233 #define KBASE_REG_GPU_NX (1ul << 3)
235 #define KBASE_REG_CPU_CACHED (1ul << 4)
237 #define KBASE_REG_GPU_CACHED (1ul << 5)
239 #define KBASE_REG_GROWABLE (1ul << 6)
241 #define KBASE_REG_PF_GROW (1ul <<
[all...]
H A Dmali_midg_regmap.h583 #define SC_ALT_COUNTERS (1ul << 3)
584 #define SC_OVERRIDE_FWD_PIXEL_KILL (1ul << 4)
585 #define SC_SDC_DISABLE_OQ_DISCARD (1ul << 6)
586 #define SC_LS_ALLOW_ATTR_TYPES (1ul << 16)
587 #define SC_LS_PAUSEBUFFER_DISABLE (1ul << 16)
588 #define SC_LS_ATTR_CHECK_DISABLE (1ul << 18)
589 #define SC_ENABLE_TEXGRD_FLAGS (1ul << 25)
594 #define TC_CLOCK_GATE_OVERRIDE (1ul << 0)
600 #define JM_TIMESTAMP_OVERRIDE (1ul << 0)
601 #define JM_CLOCK_GATE_OVERRIDE (1ul <<
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_kbase_mem.h97 #define KBASE_MEM_PHY_ALLOC_ACCESSED_CACHED (1ul << 0)
98 #define KBASE_MEM_PHY_ALLOC_LARGE (1ul << 1)
227 #define KBASE_REG_FREE (1ul << 0)
229 #define KBASE_REG_CPU_WR (1ul << 1)
231 #define KBASE_REG_GPU_WR (1ul << 2)
233 #define KBASE_REG_GPU_NX (1ul << 3)
235 #define KBASE_REG_CPU_CACHED (1ul << 4)
237 #define KBASE_REG_GPU_CACHED (1ul << 5)
239 #define KBASE_REG_GROWABLE (1ul << 6)
241 #define KBASE_REG_PF_GROW (1ul <<
[all...]
H A Dmali_midg_regmap.h583 #define SC_ALT_COUNTERS (1ul << 3)
584 #define SC_OVERRIDE_FWD_PIXEL_KILL (1ul << 4)
585 #define SC_SDC_DISABLE_OQ_DISCARD (1ul << 6)
586 #define SC_LS_ALLOW_ATTR_TYPES (1ul << 16)
587 #define SC_LS_PAUSEBUFFER_DISABLE (1ul << 16)
588 #define SC_LS_ATTR_CHECK_DISABLE (1ul << 18)
589 #define SC_ENABLE_TEXGRD_FLAGS (1ul << 25)
594 #define TC_CLOCK_GATE_OVERRIDE (1ul << 0)
600 #define JM_TIMESTAMP_OVERRIDE (1ul << 0)
601 #define JM_CLOCK_GATE_OVERRIDE (1ul <<
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_mem.h335 #define KBASE_REG_FREE (1ul << 0)
337 #define KBASE_REG_CPU_WR (1ul << 1)
339 #define KBASE_REG_GPU_WR (1ul << 2)
341 #define KBASE_REG_GPU_NX (1ul << 3)
343 #define KBASE_REG_CPU_CACHED (1ul << 4)
348 #define KBASE_REG_GPU_CACHED (1ul << 5)
350 #define KBASE_REG_GROWABLE (1ul << 6)
352 #define KBASE_REG_PF_GROW (1ul << 7)
355 #define KBASE_REG_GPU_VA_SAME_4GB_PAGE (1ul << 8)
358 #define KBASE_REG_SHARE_IN (1ul <<
[all...]
/device/qemu/arm_mps3_an547/liteos_m/board/driver/
H A Darm_uart_drv.c38 #define ARM_UART_TX_EN (1ul << 0)
39 #define ARM_UART_RX_EN (1ul << 1)
40 #define ARM_UART_TX_INTR_EN (1ul << 2)
41 #define ARM_UART_RX_INTR_EN (1ul << 3)
44 #define ARM_UART_TX_BF (1ul << 0)
45 #define ARM_UART_RX_BF (1ul << 1)
48 #define ARM_UART_TX_INTR (1ul << 0)
49 #define ARM_UART_RX_INTR (1ul << 1)
52 #define ARM_UART_INITIALIZED (1ul << 0)
/device/qemu/arm_mps2_an386/liteos_m/board/driver/
H A Darm_uart_drv.c38 #define ARM_UART_TX_EN (1ul << 0)
39 #define ARM_UART_RX_EN (1ul << 1)
40 #define ARM_UART_TX_INTR_EN (1ul << 2)
41 #define ARM_UART_RX_INTR_EN (1ul << 3)
44 #define ARM_UART_TX_BF (1ul << 0)
45 #define ARM_UART_RX_BF (1ul << 1)
48 #define ARM_UART_TX_INTR (1ul << 0)
49 #define ARM_UART_RX_INTR (1ul << 1)
52 #define ARM_UART_INITIALIZED (1ul << 0)
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_kbase_mem.h282 #define KBASE_REG_FREE (1ul << 0)
284 #define KBASE_REG_CPU_WR (1ul << 1)
286 #define KBASE_REG_GPU_WR (1ul << 2)
288 #define KBASE_REG_GPU_NX (1ul << 3)
290 #define KBASE_REG_CPU_CACHED (1ul << 4)
295 #define KBASE_REG_GPU_CACHED (1ul << 5)
297 #define KBASE_REG_GROWABLE (1ul << 6)
299 #define KBASE_REG_PF_GROW (1ul << 7)
302 #define KBASE_REG_GPU_VA_SAME_4GB_PAGE (1ul << 8)
305 #define KBASE_REG_SHARE_IN (1ul <<
[all...]
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/csf/
H A Dmali_base_csf_kernel.h189 #define BASEP_MEM_INVALID_HANDLE (0ul)
190 #define BASE_MEM_MMU_DUMP_HANDLE (1ul << LOCAL_PAGE_SHIFT)
191 #define BASE_MEM_TRACE_BUFFER_HANDLE (2ul << LOCAL_PAGE_SHIFT)
192 #define BASE_MEM_MAP_TRACKING_HANDLE (3ul << LOCAL_PAGE_SHIFT)
193 #define BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE (4ul << LOCAL_PAGE_SHIFT)
195 #define BASEP_MEM_CSF_USER_REG_PAGE_HANDLE (47ul << LOCAL_PAGE_SHIFT)
196 #define BASEP_MEM_CSF_USER_IO_PAGES_HANDLE (48ul << LOCAL_PAGE_SHIFT)
197 #define BASE_MEM_COOKIE_BASE (64ul << LOCAL_PAGE_SHIFT)
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_defs.h49 #define CSF_FIRMWARE_ENTRY_READ (1ul << 0)
50 #define CSF_FIRMWARE_ENTRY_WRITE (1ul << 1)
51 #define CSF_FIRMWARE_ENTRY_EXECUTE (1ul << 2)
52 #define CSF_FIRMWARE_ENTRY_CACHE_MODE (3ul << 3)
53 #define CSF_FIRMWARE_ENTRY_PROTECTED (1ul << 5)
54 #define CSF_FIRMWARE_ENTRY_SHARED (1ul << 30)
55 #define CSF_FIRMWARE_ENTRY_ZERO (1ul << 31)
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/jm/
H A Dmali_base_jm_kernel.h195 #define BASEP_MEM_INVALID_HANDLE (0ul)
196 #define BASE_MEM_MMU_DUMP_HANDLE (1ul << LOCAL_PAGE_SHIFT)
197 #define BASE_MEM_TRACE_BUFFER_HANDLE (2ul << LOCAL_PAGE_SHIFT)
198 #define BASE_MEM_MAP_TRACKING_HANDLE (3ul << LOCAL_PAGE_SHIFT)
199 #define BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE (4ul << LOCAL_PAGE_SHIFT)
201 #define BASE_MEM_COOKIE_BASE (64ul << LOCAL_PAGE_SHIFT)
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h408 #define SC_LS_ALLOW_ATTR_TYPES (1ul << 16)
409 #define SC_TLS_HASH_ENABLE (1ul << 17)
410 #define SC_LS_ATTR_CHECK_DISABLE (1ul << 18)
411 #define SC_VAR_ALGORITHM (1ul << 29)
415 #define TC_CLOCK_GATE_OVERRIDE (1ul << 0)
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/csf/
H A Dmali_base_csf_kernel.h190 #define BASEP_MEM_CSF_USER_REG_PAGE_HANDLE (47ul << 12)
191 #define BASEP_MEM_CSF_USER_IO_PAGES_HANDLE (48ul << 12)
192 #define BASE_MEM_COOKIE_BASE (64ul << 12)
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/backend/
H A Dmali_kbase_gpu_regmap_jm.h258 #define JM_TIMESTAMP_OVERRIDE (1ul << 0)
259 #define JM_CLOCK_GATE_OVERRIDE (1ul << 1)
260 #define JM_JOB_THROTTLE_ENABLE (1ul << 2)
H A Dmali_kbase_gpu_regmap_csf.h214 #define GPU_FAULTSTATUS_ADDR_VALID_FLAG (1ul << GPU_FAULTSTATUS_ADDR_VALID_SHIFT)
217 #define GPU_FAULTSTATUS_JASID_VALID_FLAG (1ul << GPU_FAULTSTATUS_JASID_VALID_SHIFT)
/device/soc/hisilicon/common/hal/display/source/display_device/src/vsync/
H A Dsorft_vsync.cpp62 std::unique_lock<std::mutex> ul(mutext_); in CheckRuning()
63 condition_.wait(ul, [this]() { return (enable_ || !running_); }); in CheckRuning()
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h441 #define SC_LS_ALLOW_ATTR_TYPES (1ul << 16)
442 #define SC_TLS_HASH_ENABLE (1ul << 17)
443 #define SC_LS_ATTR_CHECK_DISABLE (1ul << 18)
444 #define SC_VAR_ALGORITHM (1ul << 29)
448 #define TC_CLOCK_GATE_OVERRIDE (1ul << 0)
457 #define L2_CONFIG_ASN_HASH_ENABLE_MASK (1ul << L2_CONFIG_ASN_HASH_ENABLE_SHIFT)
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/lwip_sack/include/lwip/
H A Dip_addr.h81 #define IPADDR4_INIT(u32val) { { { { u32val, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V4 }
92 #define IPADDR_ANY_TYPE_INIT { { { { 0ul, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_ANY }
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/backend/
H A Dmali_kbase_gpu_regmap_jm.h246 #define JM_TIMESTAMP_OVERRIDE (1ul << 0)
247 #define JM_CLOCK_GATE_OVERRIDE (1ul << 1)
248 #define JM_JOB_THROTTLE_ENABLE (1ul << 2)
/device/soc/hisilicon/common/hal/display/source/display_device/src/drm/
H A Ddrm_vsync_worker.cpp67 std::unique_lock<std::mutex> ul(mMutex); in WaitSignalAndCheckRuning()
68 mCondition.wait(ul, [this]() { return (mEnable || !mRunning); }); in WaitSignalAndCheckRuning()
/device/soc/rockchip/common/hardware/display/src/display_device/
H A Ddrm_vsync_worker.cpp69 std::unique_lock<std::mutex> ul(mMutex); in WaitSignalAndCheckRuning()
70 mCondition.wait(ul, [this]() { return (mEnable || !mRunning); }); in WaitSignalAndCheckRuning()
/device/soc/rockchip/rk3399/hardware/display/src/display_device/
H A Ddrm_vsync_worker.cpp67 std::unique_lock<std::mutex> ul(mMutex); in WaitSignalAndCheckRuning()
68 mCondition.wait(ul, [this]() { return (mEnable || !mRunning); }); in WaitSignalAndCheckRuning()
/device/soc/rockchip/rk3566/hardware/display/src/display_device/
H A Ddrm_vsync_worker.cpp67 std::unique_lock<std::mutex> ul(mMutex); in WaitSignalAndCheckRuning()
68 mCondition.wait(ul, [this]() { return (mEnable || !mRunning); }); in WaitSignalAndCheckRuning()
/device/soc/rockchip/rk3568/hardware/display/src/display_device/
H A Ddrm_vsync_worker.cpp67 std::unique_lock<std::mutex> ul(mMutex); in WaitSignalAndCheckRuning()
68 mCondition.wait(ul, [this]() { return (mEnable || !mRunning); }); in WaitSignalAndCheckRuning()
/device/soc/rockchip/rk3588/hardware/display/src/display_device/
H A Ddrm_vsync_worker.cpp67 std::unique_lock<std::mutex> ul(mMutex); in WaitSignalAndCheckRuning()
68 mCondition.wait(ul, [this]() { return (mEnable || !mRunning); }); in WaitSignalAndCheckRuning()

Completed in 25 milliseconds

123