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Searched refs:reset (Results 1 - 25 of 177) sorted by relevance

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/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_reset_gpu.c33 /* Waiting timeout for GPU reset to complete */
61 * DOC: Mechanism for coherent access to the HW with respect to GPU reset
63 * Access to the HW from non-atomic context outside of the reset thread must
66 * This currently works by taking the &kbase_device's csf.reset.sem, for
67 * 'write' access by the GPU reset thread and 'read' access by every other
71 * reset ('writer') and threads trying to access the GPU for 'normal'
74 * - multiple threads may prevent reset from happening without serializing each
75 * other prematurely. Note that at present the wait for reset to finish has
83 * If instead &kbase_device's csf.reset.wait &wait_queue_head_t were used on
88 * Indeed places where we wait on &kbase_device's csf.reset
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/sysd/arch/hi3516cv500/include/
H A Dsys_hal.h38 hi_s32 sys_hal_vi_bus_reset(hi_bool reset);
40 hi_s32 sys_hal_vi_ppc_reset(hi_bool reset);
43 hi_s32 sys_hal_vi_port_reset(hi_vi_dev dev, hi_bool reset);
48 hi_s32 sys_hal_vi_isp_cfg_reset(hi_vi_pipe pipe, hi_bool reset);
49 hi_s32 sys_hal_vi_isp_core_reset(hi_vi_pipe pipe, hi_bool reset);
52 hi_s32 sys_hal_vi_proc_reset(hi_s32 vi_proc, hi_bool reset);
72 hi_s32 sys_hal_vou_bus_reset_sel(hi_bool reset);
104 hi_s32 sys_hal_vedu_reset_sel(hi_s32 vedu, hi_bool reset);
110 hi_s32 sys_hal_vpss_reset_sel(hi_s32 vpss, hi_bool reset);
117 hi_s32 sys_hal_avs_reset_sel(hi_bool reset);
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/hdfadapt/
H A Dhdfinit_3881.c44 if (device->reset != NULL && device->reset->Reset != NULL) { in InitHi3881Chip()
45 device->reset->Reset(device->reset); in InitHi3881Chip()
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/sysd/arch/hi3516cv500/hal/
H A Dsys_drv.c109 hi_bool *reset = HI_NULL; in sys_drv_drv_ioctrl() local
110 reset = (hi_bool *)io_args; in sys_drv_drv_ioctrl()
111 sys_hal_vou_bus_reset_sel(*reset); in sys_drv_drv_ioctrl()
280 hi_bool *reset = HI_NULL; in sys_drv_drv_ioctrl() local
281 reset = (hi_bool *)io_args; in sys_drv_drv_ioctrl()
282 sys_hal_aio_reset_sel(*reset); in sys_drv_drv_ioctrl()
H A Dsys_hal.c76 hi_s32 sys_hal_vou_bus_reset_sel(hi_bool reset) in sys_hal_vou_bus_reset_sel() argument
78 hi_u32 tmp = (reset == HI_TRUE) ? 1 : 0; in sys_hal_vou_bus_reset_sel()
90 hi_reg_set_bit(tmp, 1, io_crg_address(VOU_CRG_PERCTL_ADDR)); /* 1:vo software reset clock */ in sys_hal_vou_apb_clk_en()
324 hi_s32 sys_hal_aio_reset_sel(hi_bool reset) in sys_hal_aio_reset_sel() argument
326 hi_u32 tmp = (reset == HI_TRUE) ? 1 : 0; in sys_hal_aio_reset_sel()
328 hi_reg_set_bit(tmp, 0, io_crg_address(CRG_PERCTL103_ADDR)); /* 0:software reset */ in sys_hal_aio_reset_sel()
329 hi_reg_set_bit(tmp, 2, io_crg_address(CRG_PERCTL103_ADDR)); /* 2:pop reset */ in sys_hal_aio_reset_sel()
/device/soc/rockchip/rk3566/sdk_linux/drivers/iio/adc/
H A Drockchip_saradc.c16 #include <linux/reset.h>
53 struct reset_control *reset; member
241 static void rockchip_saradc_reset_controller(struct reset_control *reset) in rockchip_saradc_reset_controller() argument
243 reset_control_assert(reset); in rockchip_saradc_reset_controller()
245 reset_control_deassert(reset); in rockchip_saradc_reset_controller()
414 * The reset should be an optional property, as it should work in rockchip_saradc_probe()
417 info->reset = devm_reset_control_get_exclusive(&pdev->dev, "saradc-apb"); in rockchip_saradc_probe()
418 if (IS_ERR(info->reset)) { in rockchip_saradc_probe()
419 ret = PTR_ERR(info->reset); in rockchip_saradc_probe()
424 dev_dbg(&pdev->dev, "no reset contro in rockchip_saradc_probe()
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/device/soc/rockchip/common/vendor/drivers/net/
H A Drfkill-bt.c272 struct rfkill_rk_gpio *reset = &rfkill->pdata->reset_gpio; in rfkill_rk_set_power() local
319 if (gpio_is_valid(reset->io)) { in rfkill_rk_set_power()
320 if (gpio_get_value(reset->io) == !reset->enable) { in rfkill_rk_set_power()
321 gpio_direction_output(reset->io, !reset->enable); in rfkill_rk_set_power()
323 gpio_direction_output(reset->io, reset->enable); in rfkill_rk_set_power()
350 if (gpio_is_valid(reset->io)) { in rfkill_rk_set_power()
351 if (gpio_get_value(reset in rfkill_rk_set_power()
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H A Drfkill-wlan.c228 struct rksdmmc_gpio *poweron, *reset; in rockchip_wifi_power() local
286 reset = &mrfkill->pdata->reset_n; in rockchip_wifi_power()
299 if (gpio_is_valid(reset->io)) { in rockchip_wifi_power()
300 gpio_direction_output(reset->io, reset->enable); in rockchip_wifi_power()
313 if (gpio_is_valid(reset->io)) { in rockchip_wifi_power()
314 gpio_direction_output(reset->io, !(reset->enable)); in rockchip_wifi_power()
/device/soc/rockchip/rk3588/kernel/net/rfkill/
H A Drfkill-bt.c283 struct rfkill_rk_gpio *reset = &rfkill->pdata->reset_gpio; in rfkill_rk_set_power() local
331 if (gpio_is_valid(reset->io)) { in rfkill_rk_set_power()
332 if (gpio_get_value(reset->io) == !reset->enable) { in rfkill_rk_set_power()
333 gpio_direction_output(reset->io, in rfkill_rk_set_power()
334 !reset->enable); in rfkill_rk_set_power()
336 gpio_direction_output(reset->io, reset->enable); in rfkill_rk_set_power()
364 if (gpio_is_valid(reset->io)) { in rfkill_rk_set_power()
365 if (gpio_get_value(reset in rfkill_rk_set_power()
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H A Drfkill-wlan.c230 struct rksdmmc_gpio *poweron, *reset; in rockchip_wifi_power() local
289 reset = &mrfkill->pdata->reset_n; in rockchip_wifi_power()
302 if (gpio_is_valid(reset->io)) { in rockchip_wifi_power()
303 gpio_direction_output(reset->io, reset->enable); in rockchip_wifi_power()
316 if (gpio_is_valid(reset->io)) { in rockchip_wifi_power()
317 gpio_direction_output(reset->io, !(reset->enable)); in rockchip_wifi_power()
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/
H A Dstart.S17 b reset
55 * the actual reset code
58 reset: label
145 ldr r1, rstctl @ get addr for global reset
147 mov r3, #0x2 @ full reset pll + mpu
148 str r3, [r1] @ force reset
196 /* reset */
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A Dstart.S17 b reset
55 * the actual reset code
58 reset: label
145 ldr r1, rstctl @ get addr for global reset
147 mov r3, #0x2 @ full reset pll + mpu
148 str r3, [r1] @ force reset
196 /* reset */
/device/board/hihope/rk3568/wifi/bcmdhd_wifi6/hdfadapt/
H A Dhdf_driver_bdh_register.c53 if (wlanDevice && strcmp(wlanDevice->driverName, BDH6_DRIVER_NAME) == 0 && wlanDevice->reset) { in BDH6_ResetDriver()
59 ret = wlanDevice->reset->Reset(wlanDevice->reset); in BDH6_ResetDriver()
/device/soc/hisilicon/common/hal/display/source/display_gralloc/src/
H A Dallocator_manager.cpp61 frameBufferAllocator_.reset(); in DeInit()
62 allocator_.reset(); in DeInit()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/startup/
H A Dmain.c66 reset(); in start_loaderboot()
82 reset(); in start_loaderboot()
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/ispp/
H A Dhw.c16 #include <linux/reset.h>
46 if (hw->reset) { in rkispp_soft_reset()
47 reset_control_assert(hw->reset); in rkispp_soft_reset()
49 reset_control_deassert(hw->reset); in rkispp_soft_reset()
53 /* refresh iommu after reset */ in rkispp_soft_reset()
371 hw_dev->reset = devm_reset_control_array_get(dev, false, false); in rkispp_hw_probe()
372 if (IS_ERR(hw_dev->reset)) { in rkispp_hw_probe()
373 dev_info(dev, "failed to get cru reset\n"); in rkispp_hw_probe()
374 hw_dev->reset = NULL; in rkispp_hw_probe()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/ispp/
H A Dhw.c16 #include <linux/reset.h>
47 if (hw->reset) { in rkispp_soft_reset()
48 reset_control_assert(hw->reset); in rkispp_soft_reset()
50 reset_control_deassert(hw->reset); in rkispp_soft_reset()
54 /* refresh iommu after reset */ in rkispp_soft_reset()
379 hw_dev->reset = devm_reset_control_array_get(dev, false, false); in rkispp_hw_probe()
380 if (IS_ERR(hw_dev->reset)) { in rkispp_hw_probe()
381 dev_info(dev, "failed to get cru reset\n"); in rkispp_hw_probe()
382 hw_dev->reset = NULL; in rkispp_hw_probe()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_mode_config.c180 * drm_mode_config_reset - call ->reset callbacks
183 * This functions calls all the crtc's, encoder's and connector's ->reset
185 * reset hardware and software state.
195 drm_for_each_plane(plane, dev) if (plane->funcs->reset) plane->funcs->reset(plane); in drm_mode_config_reset()
197 drm_for_each_crtc(crtc, dev) if (crtc->funcs->reset) crtc->funcs->reset(crtc); in drm_mode_config_reset()
199 drm_for_each_encoder(encoder, dev) if (encoder->funcs->reset) encoder->funcs->reset(encoder); in drm_mode_config_reset()
202 drm_for_each_connector_iter(connector, &conn_iter) if (connector->funcs->reset) connecto in drm_mode_config_reset()
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/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c27 #include <linux/reset.h>
145 struct reset_control *reset; member
377 if (phy->reset) { in rockchip_usb_phy_reset()
378 reset_control_assert(phy->reset); in rockchip_usb_phy_reset()
380 reset_control_deassert(phy->reset); in rockchip_usb_phy_reset()
389 .reset = rockchip_usb_phy_reset,
759 rk_phy->reset = of_reset_control_get(child, "phy-reset"); in rockchip_usb_phy_init()
760 if (IS_ERR(rk_phy->reset)) { in rockchip_usb_phy_init()
761 rk_phy->reset in rockchip_usb_phy_init()
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/device/soc/rockchip/common/sdk_linux/drivers/thermal/
H A Drockchip_thermal.c17 #include <linux/reset.h>
39 * the resulting TSHUT gave CRU module,let it reset the entire chip,
164 * @reset: the reset controller of tsadc
182 struct reset_control *reset; member
1384 * Reset TSADC Controller, reset all tsadc registers.
1385 * @reset: the reset controller of tsadc
1387 static void rockchip_thermal_reset_controller(struct reset_control *reset) in rockchip_thermal_reset_controller() argument
1389 reset_control_assert(reset); in rockchip_thermal_reset_controller()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/mbedtls/include/mbedtls/
H A Dtiming.h83 * \param reset If 0, query the elapsed time. Otherwise (re)start the timer.
85 * \return Elapsed time since the previous reset in ms. When
88 * \note To initialize a timer, call this function with reset=1.
94 * the delay since the first reset.
96 unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int reset );
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_osk_specific.h58 void mali_init_cpu_time_counters(int reset, int enable_divide_by_64);
/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_osk_specific.h58 void mali_init_cpu_time_counters(int reset, int enable_divide_by_64);
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Dhw.c17 #include <linux/reset.h>
654 /* if isp working, cru reset isn't secure. in rkisp_soft_reset()
655 * isp soft reset first to protect isp reset. in rkisp_soft_reset()
664 if (dev->reset) { in rkisp_soft_reset()
665 reset_control_assert(dev->reset); in rkisp_soft_reset()
667 reset_control_deassert(dev->reset); in rkisp_soft_reset()
671 /* reset for Dehaze */ in rkisp_soft_reset()
681 /* refresh iommu after reset */ in rkisp_soft_reset()
885 hw_dev->reset in rkisp_hw_probe()
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/panel/
H A Dpanel-ilitek-ili9881c.c53 struct gpio_desc *reset; member
295 /* And reset it */ in ili9881c_prepare()
296 gpiod_set_value(ctx->reset, 1); in ili9881c_prepare()
299 gpiod_set_value(ctx->reset, 0); in ili9881c_prepare()
358 gpiod_set_value(ctx->reset, 1); in ili9881c_unprepare()
449 ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); in ili9881c_dsi_probe()
450 if (IS_ERR(ctx->reset)) { in ili9881c_dsi_probe()
451 dev_err(&dsi->dev, "Couldn't get our reset GPIO\n"); in ili9881c_dsi_probe()
452 return PTR_ERR(ctx->reset); in ili9881c_dsi_probe()
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