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Searched refs:regval (Results 1 - 15 of 15) sorted by relevance

/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dflash.h55 unsigned int regval; \
57 regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \
58 boot_mode = GET_SPI_NOR_ADDR_MODE(regval); \
160 unsigned int old_val, regval; in hifmc100_set_system_clock() local
162 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_set_system_clock()
164 regval &= ~FMC_CLK_SEL_MASK; in hifmc100_set_system_clock()
167 regval |= clock & FMC_CLK_SEL_MASK; in hifmc100_set_system_clock()
169 regval |= FMC_CLK_SEL(FMC_CLK_24M); /* Default Clock */ in hifmc100_set_system_clock()
174 regval |= FMC_CLK_ENABLE; in hifmc100_set_system_clock()
176 regval in hifmc100_set_system_clock()
216 unsigned int old_val, regval; hifmc100_nand_clk_enable() local
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H A Dspinor.h52 unsigned int regval = readl(PERI_CRG48); in hisfc350_set_system_clock() local
54 regval = regval & (~SFC_CLSEL_MASK); in hisfc350_set_system_clock()
57 regval &= ~SFC_CLSEL_MASK; in hisfc350_set_system_clock()
58 regval |= clock & SFC_CLSEL_MASK; in hisfc350_set_system_clock()
60 regval &= ~SFC_CLSEL_MASK; in hisfc350_set_system_clock()
61 regval |= PERI_CRG48_CLK_24M; /* Default Clock */ in hisfc350_set_system_clock()
65 regval |= PERI_CRG48_CLKEN; in hisfc350_set_system_clock()
67 if (regval != readl(PERI_CRG48)) in hisfc350_set_system_clock()
68 writel(regval, (PERI_CRG4 in hisfc350_set_system_clock()
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H A Dspinand.h50 unsigned regval = readl(base + CRG48); in hisnfc100_set_system_clock() local
54 regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; in hisnfc100_set_system_clock()
57 regval |= CRG48_SPI_NAND_CLK_EN; in hisnfc100_set_system_clock()
59 regval &= ~CRG48_SPI_NAND_CLK_EN; in hisnfc100_set_system_clock()
61 if (readl(base + CRG48) != regval) in hisnfc100_set_system_clock()
62 writel(regval, (base + CRG48)); in hisnfc100_set_system_clock()
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dflash.h55 unsigned int regval; \
57 regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \
58 boot_mode = GET_SPI_NOR_ADDR_MODE(regval); \
160 unsigned int old_val, regval; in hifmc100_set_system_clock() local
162 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_set_system_clock()
164 regval &= ~FMC_CLK_SEL_MASK; in hifmc100_set_system_clock()
167 regval |= clock & FMC_CLK_SEL_MASK; in hifmc100_set_system_clock()
169 regval |= FMC_CLK_SEL(FMC_CLK_24M); /* Default Clock */ in hifmc100_set_system_clock()
174 regval |= FMC_CLK_ENABLE; in hifmc100_set_system_clock()
176 regval in hifmc100_set_system_clock()
216 unsigned int old_val, regval; hifmc100_nand_clk_enable() local
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H A Dspinor.h52 unsigned int regval = readl(PERI_CRG48); in hisfc350_set_system_clock() local
54 regval = regval & (~SFC_CLSEL_MASK); in hisfc350_set_system_clock()
57 regval &= ~SFC_CLSEL_MASK; in hisfc350_set_system_clock()
58 regval |= clock & SFC_CLSEL_MASK; in hisfc350_set_system_clock()
60 regval &= ~SFC_CLSEL_MASK; in hisfc350_set_system_clock()
61 regval |= PERI_CRG48_CLK_24M; /* Default Clock */ in hisfc350_set_system_clock()
65 regval |= PERI_CRG48_CLKEN; in hisfc350_set_system_clock()
67 if (regval != readl(PERI_CRG48)) in hisfc350_set_system_clock()
68 writel(regval, (PERI_CRG4 in hisfc350_set_system_clock()
[all...]
H A Dspinand.h50 unsigned regval = readl(base + CRG48); in hisnfc100_set_system_clock() local
54 regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock; in hisnfc100_set_system_clock()
57 regval |= CRG48_SPI_NAND_CLK_EN; in hisnfc100_set_system_clock()
59 regval &= ~CRG48_SPI_NAND_CLK_EN; in hisnfc100_set_system_clock()
61 if (readl(base + CRG48) != regval) in hisnfc100_set_system_clock()
62 writel(regval, (base + CRG48)); in hisnfc100_set_system_clock()
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dsbsdio.h138 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
139 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
140 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
141 #define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
142 (alponly ? 1 : SBSDIO_HTAV(regval)))
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/device/soc/hisilicon/common/platform/mtd/hifmc100/common/
H A Dhifmc100.h266 unsigned int regval, timeout = HIFMC_CPU_WAIT_TIMEOUT; \
268 regval = HIFMC_REG_READ((cntlr), HIFMC_OP_REG_OFF); \
270 } while ((regval & HIFMC_OP_REG_OP_START) && timeout); \
272 HDF_LOGE("%s: wait cmd cpu finish timeout(0x%x)", __func__, regval); \
278 unsigned int regval, timeout = HIFMC_DMA_WAIT_TIMEOUT; \
280 regval = HIFMC_REG_READ((cntlr), HIFMC_INT_REG_OFF); \
282 } while (!(regval & HIFMC_INT_OP_DONE) && timeout); \
284 HDF_LOGE("%s: wait dma int finish timeout(0x%x)", __func__, regval); \
289 unsigned long regval, timeout = HIFMC_CPU_WAIT_TIMEOUT; \
291 regval
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/device/board/hisilicon/hispark_taurus/liteos_a/board/
H A Dboard.c95 #define CLEAR_RESET_REG_STATUS(regval) (regval) &= ~(1U << 2)
98 UINT32 regval; in release_secondary_cores() local
105 READ_UINT32(regval, PERI_CRG30_BASE); in release_secondary_cores()
106 CLEAR_RESET_REG_STATUS(regval); in release_secondary_cores()
107 WRITE_UINT32(regval, PERI_CRG30_BASE); in release_secondary_cores()
/device/soc/rockchip/common/vendor/drivers/regulator/
H A Dxz3216.c172 int regval = -1, i; in xz3216_set_ramp() local
176 regval = i; in xz3216_set_ramp()
181 if (regval < 0) { in xz3216_set_ramp()
186 return regmap_update_bits(xz3216->regmap, XZ3216_CONTR_REG1, CTL_SLEW_MASK, regval << CTL_SLEW_SHIFT); in xz3216_set_ramp()
/device/soc/rockchip/common/sdk_linux/drivers/regulator/
H A Dfan53555.c321 int regval = -1, i; in fan53555_set_ramp() local
342 regval = i; in fan53555_set_ramp()
348 if (regval < 0) { in fan53555_set_ramp()
353 return regmap_update_bits(di->regmap, di->slew_reg, di->slew_mask, regval << di->slew_shift); in fan53555_set_ramp()
/device/soc/rockchip/rk3588/kernel/drivers/media/i2c/
H A Dov13855.c97 struct regval { struct
111 const struct regval *reg_list;
152 static const struct regval ov13855_global_regs[] = {
365 static const struct regval ov13855_2112x1568_30fps_regs[] = {
576 static const struct regval ov13855_4224x3136_30fps_regs[] = {
801 static const struct regval ov13855_4224x3136_15fps_regs[] = {
1111 const struct regval *regs) in ov13855_write_array()
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_impl.c814 unsigned int regval; in ddr_ddrt_test() local
827 regval = DDRT_REG_READ(DDR_REG_BASE_DDRT + DDRT_STATUS); in ddr_ddrt_test()
829 } while ((!(regval & DDRT_TEST_DONE_MASK)) in ddr_ddrt_test()
843 if (regval & DDRT_TEST_PASS_MASK) in ddr_ddrt_test()
3076 unsigned int regval; in ddr_ac_ddrt_test() local
3083 regval = DDRT_REG_READ(DDR_REG_BASE_DDRT + DDRT_STATUS); in ddr_ac_ddrt_test()
3085 } while ((!(regval & DDRT_TEST_DONE_MASK)) in ddr_ac_ddrt_test()
3099 if (regval & DDRT_TEST_PASS_MASK) /* No error occurred, test pass. */ in ddr_ac_ddrt_test()
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_impl.c813 unsigned int regval; in ddr_ddrt_test() local
826 regval = DDRT_REG_READ(DDR_REG_BASE_DDRT + DDRT_STATUS); in ddr_ddrt_test()
828 } while ((!(regval & DDRT_TEST_DONE_MASK)) in ddr_ddrt_test()
842 if (regval & DDRT_TEST_PASS_MASK) in ddr_ddrt_test()
3078 unsigned int regval; in ddr_ac_ddrt_test() local
3085 regval = DDRT_REG_READ(DDR_REG_BASE_DDRT + DDRT_STATUS); in ddr_ac_ddrt_test()
3087 } while ((!(regval & DDRT_TEST_DONE_MASK)) in ddr_ac_ddrt_test()
3101 if (regval & DDRT_TEST_PASS_MASK) /* No error occurred, test pass. */ in ddr_ac_ddrt_test()
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Ddhd_sdio.c427 #define W_SDREG(regval, regaddr, retryvar) \
431 W_REG(bus->dhd->osh, regaddr, regval); \

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