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Searched refs:reg_tmp (Results 1 - 3 of 3) sorted by relevance

/device/soc/hisilicon/common/platform/uart/
H A Duart_pl011.c264 uint32_t reg_tmp; in Pl011ShutDown() local
283 reg_tmp = OSAL_READW(port->physBase + UART_CR); in Pl011ShutDown()
284 reg_tmp &= ~UART_CR_TX_EN; in Pl011ShutDown()
285 reg_tmp &= ~UART_CR_RX_EN; in Pl011ShutDown()
286 reg_tmp &= ~UART_CR_EN; in Pl011ShutDown()
287 OSAL_WRITEW(reg_tmp, port->physBase + UART_CR); in Pl011ShutDown()
290 reg_tmp = OSAL_READW(port->physBase + UART_LCR_H); in Pl011ShutDown()
291 reg_tmp &= ~(UART_LCR_H_BREAK); in Pl011ShutDown()
292 reg_tmp &= ~(UART_LCR_H_FIFO_EN); in Pl011ShutDown()
293 OSAL_WRITEW(reg_tmp, por in Pl011ShutDown()
[all...]
/device/qemu/drivers/uart/
H A Duart_pl011.c265 uint32_t reg_tmp; in Pl011ShutDown() local
284 reg_tmp = OSAL_READW(port->physBase + UART_CR); in Pl011ShutDown()
285 reg_tmp &= ~UART_CR_TX_EN; in Pl011ShutDown()
286 reg_tmp &= ~UART_CR_RX_EN; in Pl011ShutDown()
287 reg_tmp &= ~UART_CR_EN; in Pl011ShutDown()
288 OSAL_WRITEW(reg_tmp, port->physBase + UART_CR); in Pl011ShutDown()
291 reg_tmp = OSAL_READW(port->physBase + UART_LCR_H); in Pl011ShutDown()
292 reg_tmp &= ~(UART_LCR_H_BREAK); in Pl011ShutDown()
293 reg_tmp &= ~(UART_LCR_H_FIFO_EN); in Pl011ShutDown()
294 OSAL_WRITEW(reg_tmp, por in Pl011ShutDown()
[all...]
/device/soc/rockchip/common/vendor/drivers/video/rockchip/rga2/
H A Drga2_drv.c511 struct rga2_reg *reg, *reg_tmp; in rga2_dump() local
521 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) in rga2_dump()
525 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) in rga2_dump()

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