Lines Matching refs:reg_tmp
265 uint32_t reg_tmp;
284 reg_tmp = OSAL_READW(port->physBase + UART_CR);
285 reg_tmp &= ~UART_CR_TX_EN;
286 reg_tmp &= ~UART_CR_RX_EN;
287 reg_tmp &= ~UART_CR_EN;
288 OSAL_WRITEW(reg_tmp, port->physBase + UART_CR);
291 reg_tmp = OSAL_READW(port->physBase + UART_LCR_H);
292 reg_tmp &= ~(UART_LCR_H_BREAK);
293 reg_tmp &= ~(UART_LCR_H_FIFO_EN);
294 OSAL_WRITEW(reg_tmp, port->physBase + UART_LCR_H);