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Searched refs:readl (Results 1 - 25 of 128) sorted by relevance

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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Disp_stats_v1x.c20 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10); in rkisp1_stats_get_awb_meas_v10()
22 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10); in rkisp1_stats_get_awb_meas_v10()
35 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12); in rkisp1_stats_get_awb_meas_v12()
37 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V12); in rkisp1_stats_get_awb_meas_v12()
52 pbuf->params.ae.exp_mean[i] = (u8)readl(addr + i * 0x04); in rkisp1_stats_get_aec_meas_v10()
65 value = readl(addr + i * 0x04); in rkisp1_stats_get_aec_meas_v12()
71 value = readl(addr + i * 0x04); in rkisp1_stats_get_aec_meas_v12()
84 af->window[0].sum = readl(base_addr + CIF_ISP_AFM_SUM_A); in rkisp1_stats_get_afc_meas()
85 af->window[0].lum = readl(base_addr + CIF_ISP_AFM_LUM_A); in rkisp1_stats_get_afc_meas()
86 af->window[1].sum = readl(base_add in rkisp1_stats_get_afc_meas()
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H A Dhw.c123 err1 = readl(base + CIF_ISP_CSI0_ERR1); in mipi_irq_hdl()
124 err2 = readl(base + CIF_ISP_CSI0_ERR2); in mipi_irq_hdl()
125 err3 = readl(base + CIF_ISP_CSI0_ERR3); in mipi_irq_hdl()
132 state = readl(base + CSI2RX_ERR_STAT); in mipi_irq_hdl()
133 phy = readl(base + CSI2RX_ERR_PHY); in mipi_irq_hdl()
134 packet = readl(base + CSI2RX_ERR_PACKET); in mipi_irq_hdl()
135 overflow = readl(base + CSI2RX_ERR_OVERFLOW); in mipi_irq_hdl()
146 u32 mis_val = readl(base + CIF_MIPI_MIS); in mipi_irq_hdl()
167 mis_val = readl(base + CIF_MI_MIS); in mi_irq_hdl()
192 mis_val = readl(bas in isp_irq_hdl()
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Disp_stats_v1x.c22 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10); in rkisp1_stats_get_awb_meas_v10()
24 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10); in rkisp1_stats_get_awb_meas_v10()
42 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12); in rkisp1_stats_get_awb_meas_v12()
44 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V12); in rkisp1_stats_get_awb_meas_v12()
65 pbuf->params.ae.exp_mean[i] = (u8)readl(addr + i * 4); in rkisp1_stats_get_aec_meas_v10()
80 value = readl(addr + i * 4); in rkisp1_stats_get_aec_meas_v12()
86 value = readl(addr + i * 4); in rkisp1_stats_get_aec_meas_v12()
100 af->window[0].sum = readl(base_addr + CIF_ISP_AFM_SUM_A); in rkisp1_stats_get_afc_meas()
101 af->window[0].lum = readl(base_addr + CIF_ISP_AFM_LUM_A); in rkisp1_stats_get_afc_meas()
102 af->window[1].sum = readl(base_add in rkisp1_stats_get_afc_meas()
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H A Dhw.c133 err1 = readl(base + CIF_ISP_CSI0_ERR1); in mipi_irq_hdl()
134 err2 = readl(base + CIF_ISP_CSI0_ERR2); in mipi_irq_hdl()
135 err3 = readl(base + CIF_ISP_CSI0_ERR3); in mipi_irq_hdl()
144 state = readl(base + CSI2RX_ERR_STAT); in mipi_irq_hdl()
145 phy = readl(base + CSI2RX_ERR_PHY); in mipi_irq_hdl()
146 packet = readl(base + CSI2RX_ERR_PACKET); in mipi_irq_hdl()
147 overflow = readl(base + CSI2RX_ERR_OVERFLOW); in mipi_irq_hdl()
157 u32 mis_val = readl(base + CIF_MIPI_MIS); in mipi_irq_hdl()
179 mis_val = readl(base + CIF_MI_MIS); in mi_irq_hdl()
203 mis_val = readl(bas in isp_irq_hdl()
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/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/hi3518ev300/
H A Dlowlevel_init_v300.c38 static inline unsigned int readl(unsigned addr) in readl() function
82 #define reg_get(addr) readl(addr)
156 temp = readl(HPM_CORE_REG0); in get_hpm_value()
159 temp = readl(HPM_CORE_REG1); in get_hpm_value()
185 sysboot10.u32 = readl(HPM_CHECK_REG); in hpm_check()
208 value = readl(TSENSOR_STATUS0); in get_temperature()
241 unsigned int otp_vmin_core = readl(OTP_HPM_CORE_REG); in set_hpm_core_volt()
265 unsigned int tmp_reg = readl(SVB_VER_REG); in start_svb()
274 pwm_id = readl(SVB_PWM_SEL) & 0xf; in start_svb()
314 reg->custom.ive_ddrt_mst_sel = readl(DDR_REG_BASE_SYSCTR in ddr_boot_prepare()
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/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A Dlowlevel_init_v300.c38 static inline unsigned int readl(unsigned addr) in readl() function
82 #define reg_get(addr) readl(addr)
266 temp = readl(HPM_CORE_REG0); in get_hpm_value()
269 temp = readl(HPM_CORE_REG1); in get_hpm_value()
296 sysboot10.u32 = readl(HPM_CHECK_REG); in hpm_check()
320 unsigned int otp_vmin_core = readl(OTP_HPM_CORE_REG); in set_hpm_core_volt()
321 unsigned int chip_id = readl(SYS_CHIP_ID); in set_hpm_core_volt()
384 value = readl(REG_BASE_MISC + TSENSOR_STATUS0); in get_temperature()
411 unsigned int chip_id = readl(SYS_CHIP_ID); in start_svb()
415 unsigned int tmp_reg = readl(SVB_VER_RE in start_svb()
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/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Drockchip_debug.c94 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_edpcsr()
107 edpcsr = ((u64)readl(base + EDPCSR_LO)) | ((u64)readl(base + EDPCSR_HI) << 0x20); in rockchip_debug_dump_edpcsr()
109 edpcsr = (u32)readl(base + EDPCSR_LO); in rockchip_debug_dump_edpcsr()
147 pmpcsr = ((u64)readl(base + PMPCSR_LO)) | ((u64)readl(base + PMPCSR_HI) << 0x20); in rockchip_debug_dump_pmpcsr()
217 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_panic_notify_edpcsr()
230 edpcsr = ((u64)readl(base + EDPCSR_LO)) | ((u64)readl(base + EDPCSR_HI) << 0x20); in rockchip_panic_notify_edpcsr()
232 edpcsr = (u32)readl(bas in rockchip_panic_notify_edpcsr()
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/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Drockchip_debug.c94 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_debug_dump_edpcsr()
110 edpcsr = ((u64)readl(base + EDPCSR_LO)) | in rockchip_debug_dump_edpcsr()
111 ((u64)readl(base + EDPCSR_HI) << 32); in rockchip_debug_dump_edpcsr()
113 edpcsr = (u32)readl(base + EDPCSR_LO); in rockchip_debug_dump_edpcsr()
153 pmpcsr = ((u64)readl(base + PMPCSR_LO)) | in rockchip_debug_dump_pmpcsr()
154 ((u64)readl(base + PMPCSR_HI) << 32); in rockchip_debug_dump_pmpcsr()
224 pu = (u32)readl(base + EDPRSR) & EDPRSR_PU; in rockchip_panic_notify_edpcsr()
239 edpcsr = ((u64)readl(base + EDPCSR_LO)) | in rockchip_panic_notify_edpcsr()
240 ((u64)readl(base + EDPCSR_HI) << 32); in rockchip_panic_notify_edpcsr()
242 edpcsr = (u32)readl(bas in rockchip_panic_notify_edpcsr()
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/adapter/
H A Dhdf_wlan_sdio_adapt.c63 HDF_LOGW("%s: Change register[0x%08x] %04x to %04x", __func__, ADDR, readl(reg), (VALUE)); \
75 HDF_LOGW("%s: Change register[0x%08x] %04x to %04x", __func__, ADDR, readl(reg), readl(reg) | (VALUE)); \
76 writel(readl(reg) | (VALUE), reg); \
83 HDF_LOGW("%s: Change register[0x%08x] %04x to %04x", __func__, ADDR, readl(reg), (VALUE)); \
90 HDF_LOGW("%s: Change register[0x%08x] %04x to %04x", __func__, ADDR, readl(reg), readl(reg) | (VALUE)); \
91 writel(readl(reg) | (VALUE), reg); \
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/platform/vexpress/
H A Dmali_kbase_cpu_vexpress.c115 reg_val = readl(syscfg_reg + SYS_CFGCTRL_OFFSET); in kbase_get_vexpress_cpu_clock_speed()
133 while (!(readl(syscfg_reg + SYS_CFGSTAT_OFFSET) & in kbase_get_vexpress_cpu_clock_speed()
138 reg_val = readl(syscfg_reg + SYS_CFGSTAT_OFFSET); in kbase_get_vexpress_cpu_clock_speed()
146 osc2_value = readl(syscfg_reg + SYS_CFGDATA_OFFSET); in kbase_get_vexpress_cpu_clock_speed()
148 reg_val = readl(scc_reg); in kbase_get_vexpress_cpu_clock_speed()
236 sys_procid1 = readl(syscfg_reg); in kbase_get_platform_logic_tile_type()
/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c144 val = readl(priv->mmio + (0x19 << 0x02)); in rockchip_combphy_pcie_init()
438 val = readl(priv->mmio + (0x1f << 0x02)); in rk3568_combphy_cfg()
450 val = readl(priv->mmio + (0x1f << 0x02)); in rk3568_combphy_cfg()
456 val = readl(priv->mmio + (0x0e << 0x02)); in rk3568_combphy_cfg()
462 val = readl(priv->mmio + (0x20 << 0x02)); in rk3568_combphy_cfg()
471 val = readl(priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
520 val = readl(priv->mmio + (0x0e << 0x02)); in rk3568_combphy_cfg()
525 val = readl(priv->mmio + (0x0f << 0x02)); in rk3568_combphy_cfg()
538 val = readl(priv->mmio + (0x20 << 0x02)); in rk3568_combphy_cfg()
546 val = readl(pri in rk3568_combphy_cfg()
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/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c146 val = readl(priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
443 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
455 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
461 val = readl(priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
467 val = readl(priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
476 val = readl(priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
525 val = readl(priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
530 val = readl(priv->mmio + (0x0f << 2)); in rk3568_combphy_cfg()
543 val = readl(priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
551 val = readl(pri in rk3568_combphy_cfg()
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/device/soc/rockchip/common/sdk_linux/drivers/nvmem/
H A Drockchip-efuse.c108 writel(readl(base + RK1808_MOD) & (~RK1808_USER_MODE), base + RK1808_MOD); in rk1808_efuse_timing_init()
126 writel(readl(base + RK1808_MOD) | RK1808_USER_MODE, base + RK1808_MOD); in rk1808_efuse_timing_deinit()
174 status = readl(efuse->base + RK1808_INT_STATUS); in rockchip_rk1808_efuse_read()
179 out_value = readl(efuse->base + RK1808_DOUT); in rockchip_rk1808_efuse_read()
213 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3128_A_SHIFT)), in rockchip_rk3128_efuse_read()
215 writel(readl(efuse->base + REG_EFUSE_CTRL) | ((offset++ & RK3288_A_MASK) << RK3128_A_SHIFT), in rockchip_rk3128_efuse_read()
218 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
221 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL); in rockchip_rk3128_efuse_read()
248 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~(RK3288_A_MASK << RK3288_A_SHIFT)), in rockchip_rk3288_efuse_read()
250 writel(readl(efus in rockchip_rk3288_efuse_read()
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/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dflash.h57 regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \
91 reg_val = readl(MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
96 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
102 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
162 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_set_system_clock()
218 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_nand_clk_enable()
H A Dspinor.h45 start_up_mode = readl(IO_ADDRESS(SYS_CTRL_REG_BASE + SFC_ADDR_MODE_REG)); \
52 unsigned int regval = readl(PERI_CRG48); in hisfc350_set_system_clock()
67 if (regval != readl(PERI_CRG48)) in hisfc350_set_system_clock()
H A Dnand.h36 unsigned int reg_val = readl(PERI_CRG52); in hinfc620_clk_enable()
45 #define check_boot_type() ((readl(SYS_CTRL_REG_BASE + REG_SYSSTAT) >> 4) & 0x3);
H A Dspinand.h50 unsigned regval = readl(base + CRG48); in hisnfc100_set_system_clock()
61 if (readl(base + CRG48) != regval) in hisnfc100_set_system_clock()
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dflash.h57 regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \
91 reg_val = readl(MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
96 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
102 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
162 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_set_system_clock()
218 old_val = regval = readl(CRG_REG_BASE + REG_FMC_CRG); in hifmc100_nand_clk_enable()
H A Dspinor.h45 start_up_mode = readl(IO_ADDRESS(SYS_CTRL_REG_BASE + SFC_ADDR_MODE_REG)); \
52 unsigned int regval = readl(PERI_CRG48); in hisfc350_set_system_clock()
67 if (regval != readl(PERI_CRG48)) in hisfc350_set_system_clock()
H A Dnand.h36 unsigned int reg_val = readl(PERI_CRG52); in hinfc620_clk_enable()
45 #define check_boot_type() ((readl(SYS_CTRL_REG_BASE + REG_SYSSTAT) >> 4) & 0x3);
H A Dspinand.h50 unsigned regval = readl(base + CRG48); in hisnfc100_set_system_clock()
61 if (readl(base + CRG48) != regval) in hisnfc100_set_system_clock()
/device/soc/rockchip/common/vendor/drivers/gpio/
H A Dgpio-rockchip.c69 return readl(reg + 0x4) << 16 | readl(reg); in gpio_readl_v2()
91 value = readl(reg); in rockchip_gpio_readl()
110 data = readl(reg); in rockchip_gpio_writel_bit()
125 data = readl(bit >= 0x10 ? reg + 0x4 : reg); in rockchip_gpio_readl_bit()
128 data = readl(reg); in rockchip_gpio_readl_bit()
150 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_gpio_get()
218 cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con); in rockchip_gpio_set_debounce()
415 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_irq_set_type()
618 id = readl(ban in rockchip_get_bank_data()
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/device/soc/rockchip/common/sdk_linux/drivers/gpio/
H A Dgpio-rockchip.c69 return readl(reg + 0x4) << 16 | readl(reg); in gpio_readl_v2()
91 value = readl(reg); in rockchip_gpio_readl()
110 data = readl(reg); in rockchip_gpio_writel_bit()
125 data = readl(bit >= 0x10 ? reg + 0x4 : reg); in rockchip_gpio_readl_bit()
128 data = readl(reg); in rockchip_gpio_readl_bit()
150 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_gpio_get()
221 cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con); in rockchip_gpio_set_debounce()
418 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_irq_set_type()
621 id = readl(ban in rockchip_get_bank_data()
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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/cif/
H A Dhw.h28 #define read_cif_reg(base, addr) readl((addr) + (base))
29 #define write_cif_reg_or(base, addr, val) writel(readl((addr) + (base)) | (val), (addr) + (base))
30 #define write_cif_reg_and(base, addr, val) writel(readl((addr) + (base)) & (val), (addr) + (base))
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/cif/
H A Dhw.h30 readl((addr) + (base))
32 writel(readl((addr) + (base)) | (val), (addr) + (base))
34 writel(readl((addr) + (base)) & (val), (addr) + (base))

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