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/device/soc/rockchip/rk2206/hardware/include/lz_hardware/
H A Dpinctrl.h159 * @brief pinctrl: set pin function.
161 * @param id Indicates pin function id.
162 * @param mode Indicates pin function mode.
163 * @return Returns {@link LZ_HARDWARE_SUCCESS} if the pin function is selected successfully;
168 static inline unsigned int PinctrlInit(Pinctrl pin) in PinctrlInit() argument
170 if (pin.gpio == INVALID_GPIO) { in PinctrlInit()
174 if (LzGpioInit(pin.gpio) != LZ_HARDWARE_SUCCESS) { in PinctrlInit()
178 PinctrlSet(pin.gpio, pin.func, pin in PinctrlInit()
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/device/soc/rockchip/rk3588/kernel/drivers/pinctrl/
H A Dpinconf.h3 * Internal interface between the core pin control system and the
4 * pin config portions
22 int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
29 int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
61 static inline int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, in pinconf_set_config() argument
98 * pin config.
105 unsigned pin);
113 const char *gname, unsigned pin) in pinconf_generic_dump_pins()
111 pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s, const char *gname, unsigned pin) pinconf_generic_dump_pins() argument
H A Dcore.h3 * Core private header for the pin control subsystem
20 * struct pinctrl_dev - pin control class device
21 * @node: node to include this pin controller in the global pin controller list
22 * @desc: the pin controller descriptor supplied when initializing this pin
24 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
26 * @pin_group_tree: optionally each pin group can be stored in this radix tree
30 * @gpio_ranges: a list of GPIO ranges that is handled by this pin controlle
229 pin_desc_get(struct pinctrl_dev *pctldev, unsigned int pin) pin_desc_get() argument
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H A Dpinctrl-rk806.c46 * Different PMIC has different pin features, belowing 3 mask members are not
49 * pin that can be used as TS/GPIO, so fun_mask, dir_mask and val_mask are all
107 PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"), /* dvs1 pin */
108 PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"), /* dvs2 pin */
109 PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3") /* dvs3 pin */
421 unsigned int pin, in rk806_pinconf_get()
431 arg = rk806_gpio_get(&pci->gpio_chip, pin); in rk806_pinconf_get()
444 unsigned int pin, in rk806_pinconf_set()
458 rk806_pmx_gpio_set_direction(pctldev, NULL, pin, false); in rk806_pinconf_set()
459 rk806_gpio_set(&pci->gpio_chip, pin, ar in rk806_pinconf_set()
420 rk806_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) rk806_pinconf_get() argument
443 rk806_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) rk806_pinconf_set() argument
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H A Dpinctrl-rockchip.h295 * @pin_base: first pin number
347 * struct rockchip_mux_recalced_data: represent a pin iomux data.
349 * @pin: pin number.
356 u8 pin; member
369 * struct rockchip_mux_recalced_data: represent a pin iomux data.
371 * @pin: index at register or used to calc index.
372 * @func: the min pin.
374 * @route_offset: the max pin.
379 u8 pin; member
427 unsigned int pin; global() member
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/device/soc/rockchip/common/sdk_linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c205 .bank_num = (ID), .pin = (PIN), .func = (FUNC), .route_offset = (REG), .route_val = (VAL), \
236 * given a pin number that is local to a pin controller, find out the pin bank
237 * and the register base of the pin bank.
239 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, unsigned pin) in pin_to_bank() argument
243 while (pin >= (b->pin_base + b->nr_pins)) { in pin_to_bank()
372 .pin = PINCTRL_ROCKCHIP_ZERO,
376 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_ONE, .reg = 0x418, .bit = PINCTRL_ROCKCHIP_TWO, .mask = 0x3},
377 {.num = PINCTRL_ROCKCHIP_ONE, .pin
769 rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, int *reg, u8 *bit, int *mask) rockchip_get_recalced_mux() argument
1351 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *loc, u32 *reg, u32 *value) rockchip_get_mux_route() argument
1376 rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) rockchip_get_mux() argument
1438 rockchip_verify_mux(struct rockchip_pin_bank *bank, int pin, int mux) rockchip_verify_mux() argument
1475 rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) rockchip_set_mux() argument
2998 rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned num_configs) rockchip_pinconf_set() argument
3089 rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) rockchip_pinconf_get() argument
3356 int pin, bank, ret; rockchip_pinctrl_register() local
3492 int pin = 0; rockchip_pinctrl_get_soc_data() local
3502 int pin = 0; rockchip_pinctrl_get_soc_data() local
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H A Dpinctrl-rockchip.h74 * DEFAULT: means same regmap as pin iomux
113 * @pin_base: first pin number
158 * struct rockchip_mux_recalced_data: represent a pin iomux data.
160 * @pin: pin number.
167 u8 pin; member
174 * struct rockchip_mux_recalced_data: represent a pin iomux data.
176 * @pin: index at register or used to calc index.
177 * @func: the min pin.
179 * @route_offset: the max pin
184 u8 pin; global() member
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H A Dpinctrl-rk805.c51 * Different PMIC has different pin features, belowing 3 mask members are not
54 * pin that can be used as TS/GPIO, so fun_mask, dir_mask and val_mask are all
189 /* for rk809 only a sleep pin */
197 PINCTRL_PIN(RK817_GPIO_SLP, "gpio_slp"), /* sleep pin */
198 PINCTRL_PIN(RK817_GPIO_TS, "gpio_ts"), /* ts pin */
199 PINCTRL_PIN(RK817_GPIO_GT, "gpio_gt") /* gate pin */
229 /* for rk809 only a sleep pin */
549 static int rk805_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) in rk805_pinconf_get() argument
558 arg = rk805_gpio_get(&pci->gpio_chip, pin); in rk805_pinconf_get()
570 static int rk805_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigne argument
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/device/soc/hisilicon/hi3516dv300/sdk_linux/sample/taurus/ai_sample/interconnection_server/
H A Dhisignalling.c36 * @param pin:指定导出的引脚
38 * @berf It is used to export the pin with the specified number and use it as GPIO
39 * @param pin: Specify the exported pin
41 static int GpioExport(int pin) in GpioExport() argument
54 len = snprintf_s(buffer, sizeof(buffer), sizeof(buffer) - 1, "%d", pin); in GpioExport()
70 * @param pin:指定删除的引脚
73 * @param pin: Specifies the pin to delete
75 static int GpioUnexport(int pin) in GpioUnexport() argument
106 GpioDirection(int pin, int dir) GpioDirection() argument
142 GpioWrite(int pin, int value) GpioWrite() argument
176 GpioRead(int pin) GpioRead() argument
215 GpioEdge(int pin, int edge) GpioEdge() argument
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/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/
H A Dnetcfg_sample.c329 char *pin = "0123456789012345"; in SampleBizTask() local
334 memcpy_s(g_devPara.pin, sizeof(g_devPara.pin), pin, sizeof(g_devPara.pin)); in SampleBizTask()
/device/qemu/SmartL_E802/liteos_m/board/hals/csky_driver/src/
H A Ddw_gpio.c49 uint32_t pin_num; ///< pin number of this handle
129 * @param[in] pin the addr store the pin num.
133 static int32_t gpio_set_irq_mode(gpio_pin_handle_t pin, gpio_irq_mode_e irq_mode) in gpio_set_irq_mode() argument
135 dw_gpio_pin_priv_t *gpio_pin_priv = pin; in gpio_set_irq_mode()
187 static void gpio_irq_clear(gpio_pin_handle_t pin, uint32_t idx) in gpio_irq_clear() argument
189 dw_gpio_pin_priv_t *gpio_pin_priv = pin; in gpio_irq_clear()
206 static void gpio_irq_enable(gpio_pin_handle_t pin) in gpio_irq_enable() argument
208 dw_gpio_pin_priv_t *gpio_pin_priv = pin; in gpio_irq_enable()
228 static void gpio_irq_disable(gpio_pin_handle_t pin) in gpio_irq_disable() argument
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H A Dpinmux.c28 int32_t drv_pinmux_config(pin_name_e pin, pin_func_e pin_func) in drv_pinmux_config() argument
/device/soc/rockchip/rk3588/kernel/include/linux/
H A Dpinctrl-rockchip.h295 * @pin_base: first pin number
347 * struct rockchip_mux_recalced_data: represent a pin iomux data.
349 * @pin: pin number.
356 u8 pin; member
369 * struct rockchip_mux_recalced_data: represent a pin iomux data.
371 * @pin: index at register or used to calc index.
372 * @func: the min pin.
374 * @route_offset: the max pin.
379 u8 pin; member
427 unsigned int pin; global() member
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/device/qemu/SmartL_E802/liteos_m/board/hals/csky_driver/include/
H A Dpinmux.h30 int32_t drv_pinmux_config(pin_name_e pin, pin_func_e pin_func);
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Ddma-buf.h85 * @pin
94 * cases like scanout and not for temporary pin operations.
100 int (*pin)(struct dma_buf_attachment *attach); member
182 * access - the exporter might need to allocate or swap-in and pin the
215 * swap-in and pin the backing storage.
570 return !!dmabuf->ops->pin; in dma_buf_is_dynamic()
/device/soc/rockchip/common/sdk_linux/drivers/regulator/
H A Dcore.c79 * Management for shared enable GPIO pin
2474 /* Manage enable GPIO list. Same GPIO pin can be shared among regulators */
2477 struct regulator_enable_gpio *pin, *new_pin; in regulator_ena_gpio_request() local
2485 list_for_each_entry(pin, &regulator_ena_gpio_list, list) in regulator_ena_gpio_request()
2487 if (pin->gpiod == gpiod) { in regulator_ena_gpio_request()
2498 pin = new_pin; in regulator_ena_gpio_request()
2501 pin->gpiod = gpiod; in regulator_ena_gpio_request()
2502 list_add(&pin->list, &regulator_ena_gpio_list); in regulator_ena_gpio_request()
2505 pin->request_count++; in regulator_ena_gpio_request()
2506 rdev->ena_pin = pin; in regulator_ena_gpio_request()
2516 struct regulator_enable_gpio *pin, *n; regulator_ena_gpio_free() local
2552 struct regulator_enable_gpio *pin = rdev->ena_pin; regulator_ena_gpio_ctrl() local
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/
H A Dhi_wifi_api.h135 * Decimal only WPS pin code length.CNcomment:WPS中十进制pin码长度.CNend
1176 * @brief Start pin connect in WPS.CNcomment:WPS通过pin码连接网络.CNend
1179 * Start pin connect in WPS.CNcomment:WPS通过pin码连接网络.CNend
1182 * 2. Decimal only WPS pin code length is 8 Bytes.CNcomment:2. WPS中pin码仅限十进制，长度为8 Bytes.CNend
1183 * @param pin [IN] Type #char * pin cod
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/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_wifi_api.h135 * Decimal only WPS pin code length.CNcomment:WPS中十进制pin码长度.CNend
1180 * @brief Start pin connect in WPS.CNcomment:WPS通过pin码连接网络.CNend
1183 * Start pin connect in WPS.CNcomment:WPS通过pin码连接网络.CNend
1186 * 2. Decimal only WPS pin code length is 8 Bytes.CNcomment:2. WPS中pin码仅限十进制，长度为8 Bytes.CNend
1187 * @param pin [IN] Type #char * pin cod
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/device/soc/rockchip/common/sdk_linux/drivers/dma-buf/
H A Ddma-buf.c640 if (WARN_ON(exp_info->ops->cache_sgt_mapping && (exp_info->ops->pin || exp_info->ops->unpin))) { in dma_buf_export()
644 if (WARN_ON(!exp_info->ops->pin != !exp_info->ops->unpin)) { in dma_buf_export()
801 if (dmabuf->ops->pin) { in dma_buf_pin()
802 ret = dmabuf->ops->pin(attach); in dma_buf_pin()
/device/soc/hisilicon/hi3861v100/sdk_liteos/components/at/src/
H A Dat_wifi.c850 * Func description: get wps pin value
873 * Func description: using wps pin to connect network
878 hi_char pin[WIFI_WPS_PIN_LEN + 1] = {0}; in cmd_wpa_wps_pin() local
879 hi_char *ppin = pin; in cmd_wpa_wps_pin()
886 if ((len != WIFI_WPS_PIN_LEN) || (memcpy_s(pin, WIFI_WPS_PIN_LEN + 1, argv[0], len) != EOK)) { in cmd_wpa_wps_pin()
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dsiutils.h514 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
515 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
517 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_gem.c1207 if (obj->funcs && obj->funcs->pin) in drm_gem_pin()
1208 return obj->funcs->pin(obj); in drm_gem_pin()
/device/soc/rockchip/rk3588/kernel/drivers/gpio/
H A Dgpio-rockchip.c264 * gpiolib set_config callback function. The setting of the pin
300 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
590 * If it is present, it takes care of adding the pin ranges in rockchip_gpiolib_register()
611 dev_err(bank->dev, "Failed to add pin range\n"); in rockchip_gpiolib_register()
745 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); in rockchip_gpio_probe()
747 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, cfg->arg); in rockchip_gpio_probe()

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