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Searched refs:phys_base (Results 1 - 10 of 10) sorted by relevance

/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_mem_validation.c18 u32 phys_base; /**< Mali physical base of the memory, page aligned */ member
27 if (MALI_INVALID_MEM_ADDR != mali_mem_validator.phys_base) { in mali_mem_validation_add_range()
39 mali_mem_validator.phys_base = start; in mali_mem_validation_add_range()
42 mali_mem_validator.phys_base, mali_mem_validator.size)); in mali_mem_validation_add_range()
53 if ((phys_addr >= mali_mem_validator.phys_base) && in mali_mem_validation_check()
54 ((phys_addr + (size - 1)) >= mali_mem_validator.phys_base) && in mali_mem_validation_check()
55 (phys_addr <= (mali_mem_validator.phys_base + (mali_mem_validator.size - 1))) && in mali_mem_validation_check()
56 ((phys_addr + (size - 1)) <= (mali_mem_validator.phys_base + (mali_mem_validator.size - 1)))) { in mali_mem_validation_check()
63 MALI_PRINT_ERROR(("MALI PHYSICAL RANGE VALIDATION ERROR: The range supplied was: phys_base=0x%08X, size=0x%08X\n", phys_addr, size)); in mali_mem_validation_check()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/uart/
H A Dhi_uart.c115 hi_reg_read32(udd->phys_base + UART_FR, val); in hi_uart_is_busy()
134 hi_reg_read32(udd->phys_base + UART_FR, val); in hi_uart_is_buf_empty()
450 g_uart_regs_save[port_num].ibrd = hi_reg_read_val16(udd->phys_base + UART_IBRD); in hi_uart_lp_save()
451 g_uart_regs_save[port_num].fbrd = hi_reg_read_val16(udd->phys_base + UART_FBRD); in hi_uart_lp_save()
452 g_uart_regs_save[port_num].lcr_h = hi_reg_read_val16(udd->phys_base + UART_LCR_H); in hi_uart_lp_save()
453 g_uart_regs_save[port_num].cr = hi_reg_read_val16(udd->phys_base + UART_CR); in hi_uart_lp_save()
454 g_uart_regs_save[port_num].ifls = hi_reg_read_val16(udd->phys_base + UART_IFLS); in hi_uart_lp_save()
464 hi_u32 phys_base = ((uart_driver_data_t *) g_udd_g[port_num])->phys_base; in hi_uart_lp_restore() local
472 while ((hi_reg_read_val16(phys_base in hi_uart_lp_restore()
[all...]
H A Duart_drv.c220 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_tx_interrupt_disable()
221 hi_reg_write32(udd->phys_base + UART_IMSC, (~UART_TX_INT_BIT) & tx_status); in uart_tx_interrupt_disable()
226 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_tx_interrupt_enable()
227 hi_reg_write32(udd->phys_base + UART_IMSC, (unsigned short) (UART_TX_INT_BIT | tx_status)); in uart_tx_interrupt_enable()
232 hi_u32 int_clear_status = hi_reg_read_val32(udd->phys_base + UART_ICR); in uart_tx_interrupt_clear()
233 hi_reg_write32(udd->phys_base + UART_ICR, (unsigned short) (UART_TX_INT_BIT | int_clear_status)); in uart_tx_interrupt_clear()
238 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_rx_interrupt_disable()
239 hi_reg_write32(udd->phys_base + UART_IMSC, ~(UART_RX_INT_ENABLE) & tx_status); in uart_rx_interrupt_disable()
244 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_rx_interrupt_enable()
245 hi_reg_write32(udd->phys_base in uart_rx_interrupt_enable()
[all...]
H A Duart.c20 .phys_base = HI_UART0_REG_BASE,
37 .phys_base = HI_UART1_REG_BASE,
54 .phys_base = HI_UART2_REG_BASE,
H A Duart_drv.h163 hi_u32 phys_base; member
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
H A Dmali_mem_validation.c19 u32 phys_base; /**< Mali physical base of the memory, page aligned */ member
28 if (mali_mem_validator.phys_base != MALI_INVALID_MEM_ADDR) { in mali_mem_validation_add_range()
39 mali_mem_validator.phys_base = start; in mali_mem_validation_add_range()
43 mali_mem_validator.phys_base, mali_mem_validator.size)); in mali_mem_validation_add_range()
/device/soc/rockchip/common/sdk_linux/drivers/irqchip/
H A Dirq-gic-v3.c64 phys_addr_t phys_base; member
924 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
927 (int)(region - gic_data.redist_regions), &gic_data_rdist()->phys_base); in __gic_populate_rdist()
2011 rdist_regs[i].phys_base = res.start; in gic_of_init()
2058 static void __init gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) in gic_acpi_register_redist() argument
2062 acpi_data.redist_regs[count].phys_base = phys_base; in gic_acpi_register_redist()
H A Dirq-gic-v3-its.c102 phys_addr_t phys_base; member
1677 return its->phys_base + GITS_TRANSLATER; in its_irq_get_msi_base()
2304 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", &its->phys_base, its_base_type_string[type], in its_setup_baser()
2380 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", &its->phys_base, its_base_type_string[type], val, tmp); in its_setup_baser()
2390 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", &its->phys_base, in its_setup_baser()
2440 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", &its->phys_base, its_base_type_string[type], in its_parse_indirect_baser()
3217 target = gic_data_rdist()->phys_base; in its_cpu_init_collection()
4785 pr_err("ITS@%pa: failed to quiesce: %d\n", &its->phys_base, err); in its_save_disable()
4832 pr_err("ITS@%pa: failed to quiesce on resume: %d\n", &its->phys_base, ret); in its_restore_enable()
5018 its->phys_base in its_probe_one()
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/pci/controller/dwc/
H A Dpcie-designware.h233 phys_addr_t phys_base; member
/device/soc/rockchip/common/sdk_linux/include/linux/irqchip/
H A Darm-gic-v3.h641 phys_addr_t phys_base; member

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