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Searched refs:mux_pll_src_cpll_gpll_p (Results 1 - 4 of 4) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3368.c117 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"}; variable
324 COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5,
333 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
340 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
345 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
355 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
406 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
427 MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(14), 14, 1, MFLAGS),
434 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL, RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5,
448 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p,
[all...]
H A Dclk-rk3188.c196 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"}; variable
268 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
271 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
285 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0,
287 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
296 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
494 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
497 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
507 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
570 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICA
[all...]
H A Dclk-rk3399.c114 PNAME(mux_pll_src_cpll_gpll_p) = {"dummy_cpll", "gpll"}; variable
148 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"}; variable
495 COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7,
501 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(32), 15, 1,
504 COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7,
510 COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7,
516 COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7,
533 MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
549 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL, RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5,
687 COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p,
[all...]
H A Dclk-rk3288.c147 PNAME(mux_pll_src_cpll_gpll_p) = {"cpll", "gpll"}; variable
274 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
282 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
355 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
367 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL, RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5,
379 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
381 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
383 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
425 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
427 COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p,
[all...]

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