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Searched refs:mux_pll_p (Results 1 - 14 of 14) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3188.c193 PNAME(mux_pll_p) = {"xin24m", "xin32k"}; variable
211 PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
212 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 4, 0, NULL),
213 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), RK2928_MODE_CON, 8, 6,
215 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 7,
221 PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
222 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 5, 0, NULL),
223 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), RK2928_MODE_CON, 8, 7,
225 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 8,
H A Dclk-rk3399.c101 PNAME(mux_pll_p) = {"xin24m", "xin32k"}; variable
214 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), RK3399_PLL_CON(3), 8, 31, 0,
216 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), RK3399_PLL_CON(11), 8, 31, 0,
218 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), RK3399_PLL_CON(19), 8, 31, 0, NULL),
220 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), RK3399_PLL_CON(27), 8, 31, 0,
223 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), RK3399_PLL_CON(27), 8, 31,
226 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), RK3399_PLL_CON(35), 8, 31, 0,
228 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), RK3399_PLL_CON(43), 8, 31,
230 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), RK3399_PLL_CON(51), 8, 31, 0,
235 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, CLK_IS_CRITICA
[all...]
H A Dclk-rk3368.c112 PNAME(mux_pll_p) = {"xin24m", "xin32k"}; variable
145 [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0), RK3368_PLL_CON(3), 8, 1, 0,
147 [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4), RK3368_PLL_CON(7), 8, 0, 0,
149 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8), RK3368_PLL_CON(11), 8, 2, 0, NULL),
150 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12), RK3368_PLL_CON(15), 8, 3,
152 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16), RK3368_PLL_CON(19), 8, 4,
154 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20), RK3368_PLL_CON(23), 8, 5, 0,
H A Dclk-rk3036.c120 PNAME(mux_pll_p) = {"xin24m", "xin24m"}; variable
142 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
143 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 4, 0, NULL),
144 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 6,
H A Dclk-rk3128.c125 PNAME(mux_pll_p) = {"clk_24m", "xin24m"}; variable
154 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates),
155 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 0, 0, NULL),
157 PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates),
158 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 3,
H A Dclk-rk3328.c138 PNAME(mux_pll_p) = {"xin24m"}; variable
174 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3328_PLL_CON(0), RK3328_MODE_CON, 0, 4, 0,
176 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3328_PLL_CON(8), RK3328_MODE_CON, 4, 3, 0, NULL),
178 PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, RK3328_PLL_CON(16), RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
179 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, RK3328_PLL_CON(24), RK3328_MODE_CON, 12, 1, 0,
182 PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 0, RK3328_PLL_CON(40), RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
H A Dclk-rk3228.c126 PNAME(mux_pll_p) = {"clk_24m", "xin24m"}; variable
163 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
164 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), RK2928_MODE_CON, 4, 6, 0, NULL),
165 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), RK2928_MODE_CON, 8, 8, 0, NULL),
166 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), RK2928_MODE_CON, 12, 9,
H A Dclk-rk3288.c143 PNAME(mux_pll_p) = {"xin24m", "xin32k"}; variable
176 PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0), RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
177 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4), RK3288_MODE_CON, 4, 5, 0, NULL),
178 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8), RK3288_MODE_CON, 8, 7,
180 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8,
182 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), RK3288_MODE_CON, 14, 9,
H A Dclk-px30.c104 PNAME(mux_pll_p) = {"xin24m"}; variable
156 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, PX30_PLL_CON(0), PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
157 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, PX30_PLL_CON(8), PX30_MODE_CON, 4, 1, 0, NULL),
158 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, PX30_PLL_CON(16), PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
159 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, CLK_IS_CRITICAL, PX30_PLL_CON(24), PX30_MODE_CON, 6, 4, 0,
165 PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0), PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
H A Dclk-rv1108.c111 PNAME(mux_pll_p) = {"xin24m", "xin24m"}; variable
145 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), RV1108_PLL_CON(3), 8, 0, 0,
147 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), RV1108_PLL_CON(11), 8, 1, 0, NULL),
148 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), RV1108_PLL_CON(19), 8, 2, 0,
H A Dclk-rk3308.c99 PNAME(mux_pll_p) = {"xin24m"}; variable
159 PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3308_PLL_CON(0), RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
161 PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3308_PLL_CON(8), RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
162 [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, 0, RK3308_PLL_CON(16), RK3308_MODE_CON, 4, 2, 0,
164 [vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p, 0, RK3308_PLL_CON(24), RK3308_MODE_CON, 6, 3, 0,
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c123 PNAME(mux_pll_p) = {"xin24m", "xin32k"}; variable
178 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK1808_PLL_CON(0), RK1808_MODE_CON, 0, 0, 0, rk1808_pll_rates),
179 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK1808_PLL_CON(8), RK1808_MODE_CON, 2, 1, 0, NULL),
181 PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK1808_PLL_CON(16), RK1808_MODE_CON, 4, 2, 0, rk1808_pll_rates),
183 PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK1808_PLL_CON(24), RK1808_MODE_CON, 6, 3, 0, rk1808_pll_rates),
185 PLL(pll_rk3036, PLL_NPLL, "npll", mux_pll_p, 0, RK1808_PLL_CON(32), RK1808_MODE_CON, 8, 5, 0, rk1808_pll_rates),
186 [ppll] = PLL(pll_rk3036, PLL_PPLL, "ppll", mux_pll_p, 0, RK1808_PMU_PLL_CON(0), RK1808_PMU_MODE_CON, 0, 4, 0,
/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A Dclk-rk3568.c196 PNAME(mux_pll_p) = {"xin24m"}; variable
299 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, 0, RK3568_PMU_PLL_CON(0), RK3568_PMU_MODE_CON0, 0, 4, 0,
301 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, 0, RK3568_PMU_PLL_CON(16), RK3568_PMU_MODE_CON0, 2, 7, 0,
307 PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3568_PLL_CON(0), RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
308 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3568_PLL_CON(8), RK3568_MODE_CON0, 2, 1, 0, NULL),
309 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, RK3568_PLL_CON(24), RK3568_MODE_CON0, 4, 2, 0,
311 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, RK3568_PLL_CON(16), RK3568_MODE_CON0, 6, 3, 0,
313 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, CLK_IS_CRITICAL, RK3568_PLL_CON(32), RK3568_MODE_CON0, 10, 5,
315 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, 0, RK3568_PLL_CON(40), RK3568_MODE_CON0, 12, 6, 0,
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-rk3588.c420 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; variable
643 [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p,
646 [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p,
649 [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
652 [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p,
655 [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p,
658 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
661 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
664 [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
667 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
[all...]

Completed in 19 milliseconds