Searched refs:mux_i2s0_p (Results 1 - 4 of 4) sorted by relevance
| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 140 PNAME(mux_i2s0_p) = {"i2s0_src", "i2s0_frac", "ext_i2s", "xin12m"}; variable
167 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
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| H A D | clk-rk3328.c | 154 PNAME(mux_i2s0_p) = {"clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m"}; variable
190 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
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| H A D | clk-rk3228.c | 147 PNAME(mux_i2s0_p) = {"i2s0_src", "i2s0_frac", "ext_i2s", "xin12m"}; variable
175 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
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| H A D | clk-rk3399.c | 192 PNAME(mux_i2s0_p) = {"clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m"}; variable
248 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
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