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/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-csi2-dphy-hw.c505 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
513 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
526 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
541 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
558 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
564 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
594 val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) | in csi2_dphy_hw_stream_on()
602 val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT); in csi2_dphy_hw_stream_on()
606 val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT); in csi2_dphy_hw_stream_on()
635 if (sensor->lanes > in csi2_dphy_hw_stream_on()
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H A Dphy-rockchip-csi2-dphy.c29 int lanes; member
117 sensor->lanes = 1; in csi2_dphy_update_sensor_mbus()
120 sensor->lanes = 0x02; in csi2_dphy_update_sensor_mbus()
123 sensor->lanes = 0x03; in csi2_dphy_update_sensor_mbus()
126 sensor->lanes = 0x04; in csi2_dphy_update_sensor_mbus()
336 sensor->lanes = s_asd->lanes; in rockchip_csi2_dphy_notifier_bound()
393 s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes; in rockchip_csi2_dphy_fwnode_parse()
399 switch (s_asd->lanes) { in rockchip_csi2_dphy_fwnode_parse()
H A Dphy-rockchip-mipi-rx.c511 int lanes; member
521 int lanes; member
739 sensor->lanes = 1; in mipidphy_update_sensor_mbus()
742 sensor->lanes = 0x02; in mipidphy_update_sensor_mbus()
745 sensor->lanes = 0x03; in mipidphy_update_sensor_mbus()
748 sensor->lanes = 0x04; in mipidphy_update_sensor_mbus()
1155 write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0)); in mipidphy_rx_stream_on()
1263 * for 3288,controlled by isp,enable lanes actually in mipidphy_txrx_stream_on()
1265 * for 3399,controlled by isp1,enable lanes actually in mipidphy_txrx_stream_on()
1269 write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE, GENMASK(sensor->lanes in mipidphy_txrx_stream_on()
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H A Dphy-rockchip-naneng-edp.c90 for (lane = 0; lane < dp->lanes; lane++) { in rockchip_edp_phy_set_voltages()
136 writel(EDP_PHY_TX_PD(~GENMASK(dp->lanes - 1, 0)), edpphy->regs + EDP_PHY_GRF_CON0); in rockchip_edp_phy_set_rate()
144 writel(EDP_PHY_TX_IDLE(~GENMASK(dp->lanes - 1, 0)), edpphy->regs + EDP_PHY_GRF_CON0); in rockchip_edp_phy_set_rate()
166 switch (dp->lanes) { in rockchip_edp_phy_verify_config()
182 for (i = 0; i < dp->lanes; i++) { in rockchip_edp_phy_verify_config()
H A Dphy-rockchip-csi2-dphy-common.h50 int lanes; member
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-csi2-dphy-hw.c518 GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
526 GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
539 GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
556 GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
575 GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
582 GENMASK(sensor->lanes - 1, 0)); in csi2_dphy_config_dual_mode()
613 val |= (GENMASK(sensor->lanes - 1, 0) << in csi2_dphy_hw_stream_on()
621 val |= (GENMASK(sensor->lanes - 1, 0) << in csi2_dphy_hw_stream_on()
625 val |= (GENMASK(sensor->lanes - 1, 0) << in csi2_dphy_hw_stream_on()
655 if (sensor->lanes > in csi2_dphy_hw_stream_on()
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H A Dphy-rockchip-csi2-dphy.c29 int lanes; member
114 sensor->lanes = 1; in csi2_dphy_update_sensor_mbus()
117 sensor->lanes = 2; in csi2_dphy_update_sensor_mbus()
120 sensor->lanes = 3; in csi2_dphy_update_sensor_mbus()
123 sensor->lanes = 4; in csi2_dphy_update_sensor_mbus()
332 sensor->lanes = s_asd->lanes; in rockchip_csi2_dphy_notifier_bound()
401 s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes; in rockchip_csi2_dphy_fwnode_parse()
407 switch (s_asd->lanes) { in rockchip_csi2_dphy_fwnode_parse()
H A Dphy-rockchip-mipi-rx.c533 int lanes; member
543 int lanes; member
760 sensor->lanes = 1; in mipidphy_update_sensor_mbus()
763 sensor->lanes = 2; in mipidphy_update_sensor_mbus()
766 sensor->lanes = 3; in mipidphy_update_sensor_mbus()
769 sensor->lanes = 4; in mipidphy_update_sensor_mbus()
1183 write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0)); in mipidphy_rx_stream_on()
1292 * for 3288,controlled by isp,enable lanes actually in mipidphy_txrx_stream_on()
1294 * for 3399,controlled by isp1,enable lanes actually in mipidphy_txrx_stream_on()
1299 GENMASK(sensor->lanes in mipidphy_txrx_stream_on()
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H A Dphy-rockchip-naneng-edp.c95 for (lane = 0; lane < dp->lanes; lane++) { in rockchip_edp_phy_set_voltages()
153 writel(EDP_PHY_TX_PD(~GENMASK(dp->lanes - 1, 0)), in rockchip_edp_phy_set_rate()
163 writel(EDP_PHY_TX_IDLE(~GENMASK(dp->lanes - 1, 0)), in rockchip_edp_phy_set_rate()
187 switch (dp->lanes) { in rockchip_edp_phy_verify_config()
203 for (i = 0; i < dp->lanes; i++) { in rockchip_edp_phy_verify_config()
H A Dphy-rockchip-csi2-dphy-common.h50 int lanes; member
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Ddw-dp.c205 unsigned int lanes; member
391 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) in dw_dp_phy_xmit_enable() argument
395 switch (lanes) { in dw_dp_phy_xmit_enable()
399 xmit_enable = GENMASK(lanes - 1, 0); in dw_dp_phy_xmit_enable()
424 static bool dw_dp_bandwidth_ok(struct dw_dp *dp, const struct drm_display_mode *mode, u32 bpp, unsigned int lanes, in dw_dp_bandwidth_ok() argument
430 max_bw = lanes * rate; in dw_dp_bandwidth_ok()
522 link->lanes = 0; in dw_dp_link_reset()
623 link->lanes = min_t(u8, phy_get_bus_width(dp->phy), drm_dp_max_lane_count(link->dpcd)); in dw_dp_link_probe()
640 unsigned int lanes = link->lanes, *v in dw_dp_link_train_update_vs_emph() local
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H A Dcdn-dp-core.c160 int i, lanes; in cdn_dp_connected_port() local
164 lanes = cdn_dp_get_port_lanes(port); in cdn_dp_connected_port()
165 if (lanes) { in cdn_dp_connected_port()
263 u8 lanes, bpc; in cdn_dp_connector_mode_valid() local
284 source_max = dp->lanes; in cdn_dp_connector_mode_valid()
286 lanes = min(source_max, sink_max); in cdn_dp_connector_mode_valid()
292 actual = rate * lanes / 0x64; in cdn_dp_connector_mode_valid()
386 port->lanes = cdn_dp_get_port_lanes(port); in cdn_dp_enable_phy()
387 ret = cdn_dp_set_host_cap(dp, port->lanes, 0); in cdn_dp_enable_phy()
421 port->lanes in cdn_dp_disable_phy()
459 int ret, i, lanes; cdn_dp_enable() local
920 unsigned int lanes = dp->max_lanes; cdn_dp_pd_event_work() local
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H A Dcdn-dp-core.h57 u8 lanes; member
98 u8 lanes; member
H A Ddw-mipi-dsi2-rockchip.c268 u32 lanes; member
475 int bpp, lanes; in dw_mipi_dsi2_set_lane_rate() local
481 lanes = (dsi2->slave || dsi2->master) ? dsi2->lanes * 0x2 : dsi2->lanes; in dw_mipi_dsi2_set_lane_rate()
492 do_div(tmp, lanes); in dw_mipi_dsi2_set_lane_rate()
513 target_pclk = DIV_ROUND_CLOSEST_ULL(lane_rate * lanes, bpp); in dw_mipi_dsi2_set_lane_rate()
514 phy_mipi_dphy_get_default_config(target_pclk, bpp, lanes, &dsi2->phy_opts.mipi_dphy); in dw_mipi_dsi2_set_lane_rate()
545 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); in dw_mipi_dsi2_phy_mode_cfg()
842 dsi2->slave ? dsi2->lanes * in dw_mipi_dsi2_encoder_enable()
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/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Ddw-dp.c206 unsigned int lanes; member
410 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) in dw_dp_phy_xmit_enable() argument
414 switch (lanes) { in dw_dp_phy_xmit_enable()
418 xmit_enable = GENMASK(lanes - 1, 0); in dw_dp_phy_xmit_enable()
432 unsigned int lanes, unsigned int rate) in dw_dp_bandwidth_ok()
437 max_bw = lanes * rate; in dw_dp_bandwidth_ok()
542 link->lanes = 0; in dw_dp_link_reset()
637 link->lanes = min_t(u8, phy_get_bus_width(dp->phy), in dw_dp_link_probe()
655 unsigned int lanes = link->lanes, *v in dw_dp_link_train_update_vs_emph() local
430 dw_dp_bandwidth_ok(struct dw_dp *dp, const struct drm_display_mode *mode, u32 bpp, unsigned int lanes, unsigned int rate) dw_dp_bandwidth_ok() argument
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H A Ddw-mipi-dsi2-rockchip.c269 u32 lanes; member
471 int bpp, lanes; in dw_mipi_dsi2_set_lane_rate() local
478 lanes = (dsi2->slave || dsi2->master) ? dsi2->lanes * 2 : dsi2->lanes; in dw_mipi_dsi2_set_lane_rate()
488 do_div(tmp, lanes); in dw_mipi_dsi2_set_lane_rate()
507 target_pclk = DIV_ROUND_CLOSEST_ULL(lane_rate * lanes, bpp); in dw_mipi_dsi2_set_lane_rate()
508 phy_mipi_dphy_get_default_config(target_pclk, bpp, lanes, in dw_mipi_dsi2_set_lane_rate()
540 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); in dw_mipi_dsi2_phy_mode_cfg()
834 dsi2->slave ? dsi2->lanes * in dw_mipi_dsi2_encoder_enable()
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/device/soc/rockchip/common/sdk_linux/include/linux/phy/
H A Dphy-rockchip-typec.h11 int tcphy_dp_set_phy_config(struct phy *phy, int link_rate, int lanes, u8 swing, u8 pre_emp);
15 static inline int tcphy_dp_set_phy_config(struct phy *phy, int link_rate, int lanes, u8 swing, u8 pre_emp) in tcphy_dp_set_phy_config() argument
/device/soc/rockchip/rk3588/kernel/include/linux/phy/
H A Dphy-rockchip-typec.h11 int tcphy_dp_set_phy_config(struct phy *phy, int link_rate, int lanes,
17 int lanes, u8 swing, u8 pre_emp) in tcphy_dp_set_phy_config()
16 tcphy_dp_set_phy_config(struct phy *phy, int link_rate, int lanes, u8 swing, u8 pre_emp) tcphy_dp_set_phy_config() argument
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c243 u32 lanes; member
313 dsi->lanes = (device->lanes > max_data_lanes) ? device->lanes / 0x2 : device->lanes; in dw_mipi_dsi_host_attach()
798 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes)); in dw_mipi_dsi_dphy_interface_config()
871 /* this instance is the slave, so add the master's lanes */ in dw_mipi_dsi_get_lanes()
873 return dsi->master->lanes + dsi->lanes; in dw_mipi_dsi_get_lanes()
876 /* this instance is the master, so add the slave's lanes */ in dw_mipi_dsi_get_lanes()
890 u32 lanes = dw_mipi_dsi_get_lanes(dsi); dw_mipi_dsi_mode_set() local
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/device/soc/rockchip/common/sdk_linux/drivers/pci/controller/
H A Dpcie-rockchip.c107 rockchip->lanes = 1; in rockchip_pcie_parse_dt()
108 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); in rockchip_pcie_parse_dt()
110 (rockchip->lanes == 0 || rockchip->lanes == RK_PCIE_LANES_THREE || rockchip->lanes > RK_PCIE_LANES_FOUR)) { in rockchip_pcie_parse_dt()
111 dev_warn(dev, "invalid num-lanes, default to use one lane\n"); in rockchip_pcie_parse_dt()
112 rockchip->lanes = 1; in rockchip_pcie_parse_dt()
293 regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); in rockchip_pcie_init_port()
358 /* inactive lanes ar in rockchip_pcie_deinit_phys()
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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Dcsi.c194 int lanes, ret, i; in csi_config() local
201 lanes = 0x04; in csi_config()
204 lanes = 0x03; in csi_config()
207 lanes = 0x02; in csi_config()
210 lanes = 1; in csi_config()
247 /* lanes */ in csi_config()
248 rkisp_write(dev, CIF_ISP_CSI0_CTRL1, lanes - 1, true); in csi_config()
306 rkisp_write(dev, CSI2RX_CTRL1, lanes - 1, true); in csi_config()
364 mipi_ctrl = CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) | in csi_config()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Dcsi.c188 int lanes, ret, i; in csi_config() local
195 lanes = 4; in csi_config()
198 lanes = 3; in csi_config()
201 lanes = 2; in csi_config()
204 lanes = 1; in csi_config()
246 /* lanes */ in csi_config()
247 rkisp_write(dev, CIF_ISP_CSI0_CTRL1, lanes - 1, true); in csi_config()
309 rkisp_write(dev, CSI2RX_CTRL1, lanes - 1, true); in csi_config()
379 mipi_ctrl = CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | in csi_config()
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/cif/
H A Ddev.c948 linked_sensor.lanes = sensor->lanes; in rkcif_create_link()
953 dev->lvds_subdev.sensor_self.lanes = sensor->lanes; in rkcif_create_link()
1126 sensor->lanes = 1; in subdev_notifier_complete()
1129 sensor->lanes = NUMBER_2; in subdev_notifier_complete()
1132 sensor->lanes = NUMBER_3; in subdev_notifier_complete()
1135 sensor->lanes = NUMBER_4; in subdev_notifier_complete()
1138 sensor->lanes = 1; in subdev_notifier_complete()
1190 int lanes; member
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/cif/
H A Ddev.c1004 linked_sensor.lanes = sensor->lanes; in rkcif_create_link()
1009 dev->lvds_subdev.sensor_self.lanes = sensor->lanes; in rkcif_create_link()
1217 sensor->lanes = 1; in subdev_notifier_complete()
1220 sensor->lanes = 2; in subdev_notifier_complete()
1223 sensor->lanes = 3; in subdev_notifier_complete()
1226 sensor->lanes = 4; in subdev_notifier_complete()
1229 sensor->lanes = 1; in subdev_notifier_complete()
1281 int lanes; member
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/device/soc/rockchip/common/sdk_linux/include/drm/bridge/
H A Ddw_mipi_dsi.h33 int (*get_lane_mbps)(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes,

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