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Searched refs:cycles (Results 1 - 11 of 11) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_kbase_hwcnt_reader.h35 _IOC(_IOC_READ, KBASE_HWCNT_READER, 0x20, offsetof(struct kbase_hwcnt_reader_metadata, cycles))
38 _IOC(_IOC_WRITE, KBASE_HWCNT_READER, 0x21, offsetof(struct kbase_hwcnt_reader_metadata, cycles))
48 * struct kbase_hwcnt_reader_metadata_cycles - GPU clock cycles
49 * @top: the number of cycles associated with the main clock for the
51 * @shader_cores: the cycles that have elapsed on the GPU shader cores
63 * @cycles: the GPU cycles that occurred since the last sample
69 struct kbase_hwcnt_reader_metadata_cycles cycles; member
H A Dmali_kbase_vinstr.c218 meta->cycles.top = (clk_cnt > 0) ? dump_buf->clk_cnt_buf[0] : 0; in kbasep_vinstr_client_dump()
219 meta->cycles.shader_cores = (clk_cnt > 1) ? dump_buf->clk_cnt_buf[1] : 0; in kbasep_vinstr_client_dump()
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/
H A Dmali_kbase_hwcnt_reader.h35 offsetof(struct kbase_hwcnt_reader_metadata, cycles))
39 offsetof(struct kbase_hwcnt_reader_metadata, cycles))
51 * struct kbase_hwcnt_reader_metadata_cycles - GPU clock cycles
52 * @top: the number of cycles associated with the main clock for the
54 * @shader_cores: the cycles that have elapsed on the GPU shader cores
66 * @cycles: the GPU cycles that occurred since the last sample
72 struct kbase_hwcnt_reader_metadata_cycles cycles; member
346 /* Maximum number of domains a metadata for clock cycles can refer to */
350 * struct prfcnt_clock_metadata - Metadata for clock cycles
360 __u64 cycles[MAX_REPORTED_DOMAINS]; global() member
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/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Dhnd_pktpool.c870 uint32 cycles, i; in pktpool_start_trigger() local
879 OSL_GETCYCLES(cycles); in pktpool_start_trigger()
885 pktp->dbg_q[i].cycles = cycles; in pktpool_start_trigger()
903 uint32 cycles, i; in pktpool_stop_trigger() local
912 OSL_GETCYCLES(cycles); in pktpool_stop_trigger()
918 if (pktp->dbg_q[i].cycles == 0) in pktpool_stop_trigger()
921 if (cycles >= pktp->dbg_q[i].cycles) in pktpool_stop_trigger()
922 pktp->dbg_q[i].dur = cycles in pktpool_stop_trigger()
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/device/soc/rockchip/common/sdk_linux/drivers/clocksource/
H A Dtimer-rockchip.c69 static void rk_timer_update_counter(unsigned long cycles, struct rk_timer *timer) in rk_timer_update_counter() argument
71 writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); in rk_timer_update_counter()
80 static inline int rk_timer_set_next_event(unsigned long cycles, struct clock_event_device *ce) in rk_timer_set_next_event() argument
85 rk_timer_update_counter(cycles, timer); in rk_timer_set_next_event()
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dhnd_pktpool.h94 uint32 cycles; member
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_vinstr.c238 meta->cycles.top = (clk_cnt > 0) ? dump_buf->clk_cnt_buf[0] : 0; in kbasep_vinstr_client_dump()
239 meta->cycles.shader_cores = in kbasep_vinstr_client_dump()
H A Dmali_kbase_kinstr_prfcnt.c481 ptr_md->u.clock_md.cycles[i] = dump_buf->clk_cnt_buf[i]; in kbasep_kinstr_prfcnt_set_sample_metadata()
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/hmac/
H A Ddmac_ext_if.h882 hi_u32 cycles; /* 统计间隔时钟周期数 */ member
H A Dhmac_config.c6171 oal_io_print1("interval cycles: %u \n", thruput_info->cycles); in hmac_get_thruput_info()
/device/soc/rockchip/rk3588/kernel/drivers/media/i2c/
H A Dov13855.c1518 /* Calculate the delay in us by clock rate and clock cycles */
1519 static inline u32 ov13855_cal_delay(u32 cycles) in ov13855_cal_delay() argument
1521 return DIV_ROUND_UP(cycles, OV13855_XVCLK_FREQ / 1000 / 1000); in ov13855_cal_delay()
1567 /* 8192 cycles prior to first SCCB transaction */ in __ov13855_power_on()

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