Home
last modified time | relevance | path

Searched refs:cur_mode (Results 1 - 8 of 8) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/media/i2c/
H A Dgc2093.c153 const struct gc2093_mode *cur_mode; member
559 max = gc2093->cur_mode->height + ctrl->val - PI_REG_VALUE_FO; in gc2093_set_ctrl()
623 mode = gc2093->cur_mode; in gc2093_initialize_controls()
842 hdr_cfg->hdr_mode = gc2093->cur_mode->hdr_mode; in gc2093_ioctl()
846 w = gc2093->cur_mode->width; in gc2093_ioctl()
847 h = gc2093->cur_mode->height; in gc2093_ioctl()
851 gc2093->cur_mode = &supported_modes[i]; in gc2093_ioctl()
859 w = gc2093->cur_mode->hts_def - gc2093->cur_mode->width; in gc2093_ioctl()
860 h = gc2093->cur_mode in gc2093_ioctl()
[all...]
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_impl.c536 if (DDR_MODE_WRITE == cfg->cur_mode) { in ddr_phy_set_dq_bdl()
567 if (DDR_MODE_WRITE == cfg->cur_mode) { in ddr_phy_get_dq_bdl()
910 if (DDR_MODE_WRITE == cfg->cur_mode) in ddr_adjust_get_average()
988 if (DDR_MODE_READ == cfg->cur_mode) in ddr_adjust_get_val()
1038 if (DDR_MODE_READ == cfg->cur_mode) { in ddr_adjust_set_val()
1086 max_value = (DDR_MODE_WRITE == cfg->cur_mode ? in ddr_adjust_move_win()
1094 if (DDR_MODE_WRITE == cfg->cur_mode) in ddr_adjust_move_win()
1104 ddr_adjust_change_val(dir, &cur_val, accel, cfg->cur_mode); in ddr_adjust_move_win()
1105 if (DDR_FALSE == ddr_adjust_check_val(cur_val, cfg->cur_mode)) { in ddr_adjust_move_win()
1112 cfg->cur_byte, cfg->cur_mode, cur_va in ddr_adjust_move_win()
[all...]
H A Dddr_training_impl.h305 unsigned int cur_mode; /* read or write */ member
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_impl.c535 if (DDR_MODE_WRITE == cfg->cur_mode) { in ddr_phy_set_dq_bdl()
566 if (DDR_MODE_WRITE == cfg->cur_mode) { in ddr_phy_get_dq_bdl()
909 if (DDR_MODE_WRITE == cfg->cur_mode) in ddr_adjust_get_average()
987 if (DDR_MODE_READ == cfg->cur_mode) in ddr_adjust_get_val()
1037 if (DDR_MODE_READ == cfg->cur_mode) { in ddr_adjust_set_val()
1085 max_value = (DDR_MODE_WRITE == cfg->cur_mode ? in ddr_adjust_move_win()
1093 if (DDR_MODE_WRITE == cfg->cur_mode) in ddr_adjust_move_win()
1103 ddr_adjust_change_val(dir, &cur_val, accel, cfg->cur_mode); in ddr_adjust_move_win()
1104 if (DDR_FALSE == ddr_adjust_check_val(cur_val, cfg->cur_mode)) { in ddr_adjust_move_win()
1111 cfg->cur_byte, cfg->cur_mode, cur_va in ddr_adjust_move_win()
[all...]
H A Dddr_training_impl.h306 unsigned int cur_mode; /* read or write */ member
/device/soc/rockchip/rk3588/kernel/drivers/media/i2c/
H A Dov13855.c140 const struct ov13855_mode *cur_mode; member
1211 ov13855->cur_mode = mode; in ov13855_set_fmt()
1237 const struct ov13855_mode *mode = ov13855->cur_mode; in ov13855_get_fmt()
1306 const struct ov13855_mode *mode = ov13855->cur_mode; in ov13855_g_frame_interval()
1418 ret = ov13855_write_array(ov13855->client, ov13855->cur_mode->reg_list); in __ov13855_start_stream()
1687 sel->r.width = ov13855->cur_mode->width; in ov13855_get_selection()
1689 sel->r.height = ov13855->cur_mode->height; in ov13855_get_selection()
1748 max = ov13855->cur_mode->height + ctrl->val - 4; in ov13855_set_ctrl()
1782 ctrl->val + ov13855->cur_mode->height); in ov13855_set_ctrl()
1813 mode = ov13855->cur_mode; in ov13855_initialize_controls()
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_edid.c2155 struct drm_display_mode *t, *cur_mode, *preferred_mode; in edid_fixup_preferred() local
2172 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) in edid_fixup_preferred()
2174 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; in edid_fixup_preferred()
2176 if (cur_mode == preferred_mode) { in edid_fixup_preferred()
2181 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) { in edid_fixup_preferred()
2182 preferred_mode = cur_mode; in edid_fixup_preferred()
2185 cur_vrefresh = drm_mode_vrefresh(cur_mode); in edid_fixup_preferred()
2188 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && in edid_fixup_preferred()
2190 preferred_mode = cur_mode; in edid_fixup_preferred()
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/cmd_bin/
H A Dddr_training_cmd.c201 if (cfg->cur_mode == DDR_MODE_READ) in ddr_result_data_save()

Completed in 22 milliseconds