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/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/include/linux/mali/
H A Dmali_utgard.h73 #define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
74 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
76 #define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
77 MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
81 #define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
82 MALI_GPU_RESOURCE_L2((base_addr) + MALI400_OFFSET_L2_CACHE0) \
83 MALI_GPU_RESOURCE_GP_WITH_MMU((base_addr) + MALI_OFFSET_GP, gp_irq, (base_addr) + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
84 MALI_GPU_RESOURCE_PP_WITH_MMU(0, (base_addr) + MALI_OFFSET_PP0, pp0_irq, (base_addr)
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/include/linux/mali/
H A Dmali_utgard.h73 #define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
74 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
76 #define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
77 MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
81 #define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
82 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
83 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
84 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr
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/device/soc/hisilicon/hi3751v350/sdk_linux/source/common/drv/mmz/
H A Ddrv_tzsmmu.c43 u32 base_addr = 0; in secmem_alloc() local
45 teebuf.table = get_meminfo(phyaddr, iommu, &size, &base_addr); in secmem_alloc()
53 mem_addr.addr = base_addr; in secmem_alloc()
80 u32 base_addr = 0; in secmem_free() local
90 teebuf.table = get_meminfo(addr, iommu, &size, &base_addr); in secmem_free()
95 offset = addr - base_addr; in secmem_free()
97 sec_smmu_ref = sec_mmb_put(base_addr, iommu); in secmem_free()
111 clr_sec_mmb_flag(base_addr, iommu); in secmem_free()
113 return base_addr; in secmem_free()
131 u32 base_addr in secmem_map_to_secsmmu() local
184 u32 base_addr = 0; secmem_unmap_from_secsmmu() local
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/pwm/
H A Dpwm_drv.h27 #define pwm_en_reg(base_addr) ((base_addr)+ 0x0)
28 #define pwm_start_reg(base_addr) ((base_addr) + 0x4)
29 #define pwm_freq_reg(base_addr) ((base_addr) + 0x8)
30 #define pwm_duty_reg(base_addr) ((base_addr) + 0xC)
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/ispp/
H A Dhw.c43 writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
45 writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
59 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL); in rkispp_soft_reset()
60 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL); in rkispp_soft_reset()
61 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL); in rkispp_soft_reset()
62 writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE); in rkispp_soft_reset()
63 writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE); in rkispp_soft_reset()
64 writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL); in rkispp_soft_reset()
68 hw->base_addr + RKISPP_CTRL_INT_MSK); in rkispp_soft_reset()
69 writel(GATE_DIS_NR, hw->base_addr in rkispp_soft_reset()
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/ispp/
H A Dhw.c44 writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
46 writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET); in rkispp_soft_reset()
60 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL); in rkispp_soft_reset()
61 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL); in rkispp_soft_reset()
62 writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL); in rkispp_soft_reset()
63 writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE); in rkispp_soft_reset()
64 writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE); in rkispp_soft_reset()
65 writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL); in rkispp_soft_reset()
70 hw->base_addr + RKISPP_CTRL_INT_MSK); in rkispp_soft_reset()
71 writel(GATE_DIS_NR, hw->base_addr in rkispp_soft_reset()
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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Disp_stats_v1x.c20 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10); in rkisp1_stats_get_awb_meas_v10()
22 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10); in rkisp1_stats_get_awb_meas_v10()
35 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12); in rkisp1_stats_get_awb_meas_v12()
37 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V12); in rkisp1_stats_get_awb_meas_v12()
47 void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00_V10; in rkisp1_stats_get_aec_meas_v10()
59 void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_V12; in rkisp1_stats_get_aec_meas_v12()
77 void __iomem *base_addr; in rkisp1_stats_get_afc_meas() local
83 base_addr = stats_vdev->dev->base_addr; in rkisp1_stats_get_afc_meas()
84 af->window[0].sum = readl(base_addr in rkisp1_stats_get_afc_meas()
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H A Dhw.c114 void __iomem *base = !hw_dev->is_unite ? hw_dev->base_addr : hw_dev->base_next_addr; in mipi_irq_hdl()
160 void __iomem *base = !hw_dev->is_unite ? hw_dev->base_addr : hw_dev->base_next_addr; in mi_irq_hdl()
185 void __iomem *base = !hw_dev->is_unite ? hw_dev->base_addr : hw_dev->base_next_addr; in isp_irq_hdl()
210 mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS); in irq_handler()
212 mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS); in irq_handler()
218 mis_val = readl(hw_dev->base_addr + CIF_MIPI_MIS); in irq_handler()
223 mis_val = readl(hw_dev->base_addr + CIF_MI_MIS); in irq_handler()
651 void __iomem *base = dev->base_addr; in rkisp_soft_reset()
698 writel(val, dev->base_addr + CIF_ICCL); in isp_config_clk()
708 writel(val, dev->base_addr in isp_config_clk()
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H A Dcommon.c21 writel(val, dev->hw_dev->base_addr + reg); in rkisp_write()
44 val = readl(dev->hw_dev->base_addr + reg); in rkisp_read()
103 void IO_MEM *base = dev->hw_dev->base_addr; in rkisp_update_regs()
246 isp->base_addr = hw->base_addr; in rkisp_attach_hw()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Disp_stats_v1x.c22 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10); in rkisp1_stats_get_awb_meas_v10()
24 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10); in rkisp1_stats_get_awb_meas_v10()
42 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12); in rkisp1_stats_get_awb_meas_v12()
44 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V12); in rkisp1_stats_get_awb_meas_v12()
59 void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00_V10; in rkisp1_stats_get_aec_meas_v10()
73 void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_V12; in rkisp1_stats_get_aec_meas_v12()
93 void __iomem *base_addr; in rkisp1_stats_get_afc_meas() local
99 base_addr = stats_vdev->dev->base_addr; in rkisp1_stats_get_afc_meas()
100 af->window[0].sum = readl(base_addr in rkisp1_stats_get_afc_meas()
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H A Dhw.c125 hw_dev->base_addr : hw_dev->base_next_addr; in mipi_irq_hdl()
172 hw_dev->base_addr : hw_dev->base_next_addr; in mi_irq_hdl()
197 hw_dev->base_addr : hw_dev->base_next_addr; in isp_irq_hdl()
221 mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS); in irq_handler()
225 mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS); in irq_handler()
229 mis_val = readl(hw_dev->base_addr + CIF_MIPI_MIS); in irq_handler()
233 mis_val = readl(hw_dev->base_addr + CIF_MI_MIS); in irq_handler()
644 void __iomem *base = dev->base_addr; in rkisp_soft_reset()
688 writel(val, dev->base_addr + CIF_ICCL); in isp_config_clk()
699 writel(val, dev->base_addr in isp_config_clk()
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H A Dcommon.c21 writel(val, dev->hw_dev->base_addr + reg); in rkisp_write()
44 val = readl(dev->hw_dev->base_addr + reg); in rkisp_read()
101 void __iomem *base = dev->hw_dev->base_addr; in rkisp_update_regs()
244 isp->base_addr = hw->base_addr; in rkisp_attach_hw()
H A Dcapture_v1x.c195 void __iomem *base = stream->ispdev->base_addr; in mp_config_mi()
247 void __iomem *base = stream->ispdev->base_addr; in sp_config_mi()
297 void __iomem *base = stream->ispdev->base_addr; in mp_enable_mi()
309 void __iomem *base = stream->ispdev->base_addr; in sp_enable_mi()
317 void __iomem *base = dev->base_addr; in mp_disable_mi()
324 void __iomem *base = stream->ispdev->base_addr; in sp_disable_mi()
333 void __iomem *base = stream->ispdev->base_addr; in update_mi()
948 if (stream->ops->is_stream_stopped(dev->base_addr)) { in rkisp_mi_v1x_isr()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/common/nvm/
H A Dhi_nvm.c29 hi_u32 base_addr; member
163 nv_ctrl->base_addr = nv_info->base_addr; in nv_init_index()
173 hi_u32 nv_init_common(hi_u32 base_addr, hi_u32 total_size, hi_u32 block_size, hi_nv_type nv_type) in nv_init_common() argument
191 hi_u32 flash_addr = base_addr + i * block_size; in nv_init_common()
219 nv_info.base_addr = base_addr; in nv_init_common()
289 hi_u32 new_addr = ((nv_ctrl->current_addr + nv_ctrl->block_size) < (nv_ctrl->base_addr + nv_ctrl->total_block_size)) in nv_next_addr()
290 ? (nv_ctrl->current_addr + nv_ctrl->block_size) : (nv_ctrl->base_addr); in nv_next_addr()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/common/nvm/
H A Dhi_nvm.c28 hi_u32 base_addr; member
164 nv_ctrl->base_addr = nv_info->base_addr; in nv_init_index()
174 hi_u32 nv_init_common(hi_u32 base_addr, hi_u32 total_size, hi_u32 block_size, hi_nv_type nv_type) in nv_init_common() argument
192 hi_u32 flash_addr = base_addr + i * block_size; in nv_init_common()
220 nv_info.base_addr = base_addr; in nv_init_common()
291 hi_u32 new_addr = ((nv_ctrl->current_addr + nv_ctrl->block_size) < (nv_ctrl->base_addr + nv_ctrl->total_block_size)) in nv_next_addr()
292 ? (nv_ctrl->current_addr + nv_ctrl->block_size) : (nv_ctrl->base_addr); in nv_next_addr()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_linux_trace.h466 TP_PROTO(u64 base_addr, u64 reg_addr, u64 *gpu_mem, unsigned int flags),
467 TP_ARGS(base_addr, reg_addr, gpu_mem, flags),
469 __field(u64, base_addr)
476 __entry->base_addr = base_addr;
483 __entry->reg_addr, __entry->base_addr,
H A Dmali_kbase_kinstr_prfcnt.h113 * @base_addr: Address of allocated pages for array of samples. Used
121 u64 base_addr, u8 counter_set);
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_linux_trace.h312 mali_jit_report_gpu_mem, TP_PROTO(u64 base_addr, u64 reg_addr, u64 *gpu_mem, unsigned int flags),
313 TP_ARGS(base_addr, reg_addr, gpu_mem, flags),
314 TP_STRUCT__entry(__field(u64, base_addr) __field(u64, reg_addr)
317 TP_fast_assign(__entry->base_addr = base_addr; __entry->reg_addr = reg_addr;
320 __entry->base_addr, __print_array(__entry->mem_values, ARRAY_SIZE(__entry->mem_values), sizeof(u64)),
/device/soc/rockchip/common/hardware/rga/include/
H A Drga.h237 unsigned long base_addr; member
239 unsigned int base_addr; member
507 unsigned char cmd_flush, unsigned long base_addr, unsigned char page_size);
510 unsigned char cmd_flush, unsigned int base_addr, unsigned char page_size);
/device/soc/rockchip/rk3399/hardware/rga/include/
H A Drga.h242 unsigned long base_addr; member
244 unsigned int base_addr; member
588 unsigned long base_addr,
598 unsigned int base_addr,
/device/soc/rockchip/rk3568/hardware/rga/include/
H A Drga.h242 unsigned long base_addr; member
244 unsigned int base_addr; member
588 unsigned long base_addr,
598 unsigned int base_addr,
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Dhndmem.c147 uint32 savecore, base_addr = 0; in hndmem_mem_base() local
158 base_addr = si_get_slaveport_addr(sih, CORE_SLAVE_PORT_1, in hndmem_mem_base()
162 base_addr = 0; in hndmem_mem_base()
168 return base_addr; in hndmem_mem_base()
/device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/hack/
H A Dmpp_hack_px30.c103 mpp_err("iommu->base_addr=%08x enable failed\n", iommu->base_addr[0]); in mpp_iommu_enable()
145 if (loop->base_addr[0] == pdev->resource[0].start) { in px30_workaround_combo_init()
165 iommu->base_addr[i] = res->start; in px30_workaround_combo_init()
/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/hack/
H A Dmpp_hack_px30.c108 mpp_err("iommu->base_addr=%08x enable failed\n", in mpp_iommu_enable()
109 iommu->base_addr[0]); in mpp_iommu_enable()
153 if (loop->base_addr[0] == pdev->resource[0].start) { in px30_workaround_combo_init()
173 iommu->base_addr[i] = res->start; in px30_workaround_combo_init()
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/
H A Dhdmi_hal_intf.c622 hi_u32 *base_addr = HI_NULL; in hal_hdmi_base_addr_get() local
629 base_addr = (hi_u32 *)hal->hal_ctx.base_addr; in hal_hdmi_base_addr_get()
631 return base_addr; in hal_hdmi_base_addr_get()
744 hal->hal_ctx.base_addr = hal_init->base_addr; in hal_hdmi_open()
794 hal->hal_ctx.base_addr = HI_NULL; in hal_hdmi_close()

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