| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 24 #define SCLK_UART1 78 macro
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| H A D | rk3128-cru.h | 26 #define SCLK_UART1 78 macro
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| H A D | rk3188-cru-common.h | 21 #define SCLK_UART1 65 macro
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| H A D | rk1808-cru.h | 62 #define SCLK_UART1 61 macro
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| H A D | px30-cru.h | 26 #define SCLK_UART1 24 macro
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| H A D | rk3288-cru.h | 33 #define SCLK_UART1 78 macro
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| H A D | rk3368-cru.h | 31 #define SCLK_UART1 78 macro
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| H A D | rk3568-cru.h | 350 #define SCLK_UART1 287 macro
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| H A D | rk3399-cru.h | 40 #define SCLK_UART1 82 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 62 #define SCLK_UART1 61 macro
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| H A D | rv1126-cru.h | 25 #define SCLK_UART1 11 macro
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| H A D | rk3568-cru.h | 350 #define SCLK_UART1 287 macro
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| H A D | rk3588-cru.h | 186 #define SCLK_UART1 183 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 156 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3128.c | 179 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3368.c | 260 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
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| H A D | clk-rk3188.c | 249 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3328.c | 205 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
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| H A D | clk-rv1108.c | 161 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3228.c | 190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-rk3308.c | 288 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0, RK3308_CLKGATE_CON(2), 0, GFLAGS),
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| H A D | clk-rk3288.c | 211 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
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| H A D | clk-px30.c | 479 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 15, GFLAGS),
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 600 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0, RK1808_CLKGATE_CON(11), 11, GFLAGS),
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 891 GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0, RK3568_CLKGATE_CON(27), 15, GFLAGS),
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