| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 11 #define PLL_NPLL 5 macro
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| H A D | px30-cru.h | 10 #define PLL_NPLL 4 macro
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| H A D | rk3288-cru.h | 15 #define PLL_NPLL 5 macro
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| H A D | rk3368-cru.h | 15 #define PLL_NPLL 6 macro
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| H A D | rk3568-cru.h | 75 #define PLL_NPLL 6 macro
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| H A D | rk3399-cru.h | 16 #define PLL_NPLL 6 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 11 #define PLL_NPLL 5 macro
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| H A D | rk3568-cru.h | 75 #define PLL_NPLL 6 macro
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| H A D | rk3588-cru.h | 20 #define PLL_NPLL 8 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3368.c | 154 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20), RK3368_PLL_CON(23), 8, 5, 0,
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| H A D | clk-rk3328.c | 182 PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 0, RK3328_PLL_CON(40), RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
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| H A D | clk-rk3288.c | 182 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), RK3288_MODE_CON, 14, 9,
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| H A D | clk-px30.c | 159 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, CLK_IS_CRITICAL, PX30_PLL_CON(24), PX30_MODE_CON, 6, 4, 0,
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| H A D | clk-rk3399.c | 228 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), RK3399_PLL_CON(43), 8, 31,
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 185 PLL(pll_rk3036, PLL_NPLL, "npll", mux_pll_p, 0, RK1808_PLL_CON(32), RK1808_MODE_CON, 8, 5, 0, rk1808_pll_rates),
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 313 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, CLK_IS_CRITICAL, RK3568_PLL_CON(32), RK3568_MODE_CON0, 10, 5,
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3588.c | 664 [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
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