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Searched refs:PLL_APLL (Results 1 - 21 of 21) sorted by relevance

/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A Drk3036-cru.h11 #define PLL_APLL 1 macro
H A Drk3128-cru.h11 #define PLL_APLL 1 macro
H A Drk3188-cru-common.h11 #define PLL_APLL 1 macro
H A Drk1808-cru.h7 #define PLL_APLL 1 macro
H A Dpx30-cru.h7 #define PLL_APLL 1 macro
H A Drk3288-cru.h11 #define PLL_APLL 1 macro
H A Drk3568-cru.h70 #define PLL_APLL 1 macro
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3188.c211 PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
221 PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
651 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3066_cpuclk_data, in rk3066a_clk_init()
672 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3188_cpuclk_data, in rk3188a_clk_init()
H A Dclk-rk3036.c142 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
417 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3036_cpuclk_data, in rk3036_clk_init()
H A Dclk-rk3128.c154 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates),
509 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL_DIV2], &rk3128_cpuclk_data, in rk3128_common_clk_init()
H A Dclk-rk3328.c174 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3328_PLL_CON(0), RK3328_MODE_CON, 0, 4, 0,
654 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 4, clks[PLL_APLL], clks[PLL_GPLL], &rk3328_cpuclk_data, in rk3328_clk_init()
H A Dclk-rv1108.c145 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), RV1108_PLL_CON(3), 8, 0, 0,
578 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 3, clks[PLL_APLL], clks[PLL_GPLL], &rv1108_cpuclk_data, in rv1108_clk_init()
H A Dclk-rk3228.c163 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
557 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 3, clks[PLL_APLL], clks[PLL_GPLL], &rk3228_cpuclk_data, in rk3228_clk_init()
H A Dclk-rk3308.c159 PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3308_PLL_CON(0), RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
738 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 3, clks[PLL_APLL], clks[PLL_VPLL0], &rk3308_cpuclk_data, in rk3308_clk_init()
H A Dclk-rk3288.c176 PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0), RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
759 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3288_cpuclk_data, in rk3288_common_init()
H A Dclk-px30.c156 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, PX30_PLL_CON(0), PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
795 rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk", 2, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL], in px30_pmu_clk_init()
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/
H A Drk1808-cru.h7 #define PLL_APLL 1 macro
H A Drv1126-cru.h66 #define PLL_APLL 1 macro
H A Drk3568-cru.h70 #define PLL_APLL 1 macro
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c178 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK1808_PLL_CON(0), RK1808_MODE_CON, 0, 0, 0, rk1808_pll_rates),
870 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 3, clks[PLL_APLL], clks[PLL_GPLL], &rk1808_cpuclk_data, in rk1808_clk_init()
/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A Dclk-rk3568.c307 PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, RK3568_PLL_CON(0), RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
1186 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3568_cpuclk_data, in rk3568_clk_init()

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