Searched refs:MMU_IRQ_STATUS (Results 1 - 14 of 14) sorted by relevance
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_debug_job_fault_backend.c | 42 static int mmu_reg_snapshot[] = {MMU_IRQ_MASK, MMU_IRQ_STATUS};
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| H A D | mali_kbase_irq_linux.c | 103 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_handler()
301 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_test_handler()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_debug_job_fault_backend.c | 61 MMU_IRQ_STATUS
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| H A D | mali_kbase_irq_linux.c | 94 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_handler()
269 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_test_handler()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_debug_job_fault_backend.c | 35 static int mmu_reg_snapshot[] = {MMU_IRQ_MASK, MMU_IRQ_STATUS};
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| H A D | mali_kbase_irq_linux.c | 91 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_handler()
261 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_test_handler()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_debug_job_fault_backend.c | 65 MMU_IRQ_STATUS
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| H A D | mali_kbase_model_linux.c | 99 MMU_REG(MMU_IRQ_STATUS)))) { in serve_mmu_irq()
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| H A D | mali_kbase_irq_linux.c | 102 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_handler()
302 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_test_handler()
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| H A D | mali_kbase_model_dummy.c | 1784 } else if (addr == MMU_REG(MMU_IRQ_STATUS)) {
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 182 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ macro
237 * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 258 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ macro
304 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 261 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ macro
308 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 202 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ macro
252 * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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