| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 320 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask); in kbase_mmu_hw_clear_fault()
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 226 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask); in kbase_mmu_hw_clear_fault()
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 180 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ macro
237 * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 342 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask, kctx); in kbase_mmu_hw_clear_fault()
|
| H A D | mali_kbase_irq_linux.c | 274 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val, NULL); in kbase_mmu_irq_test_handler()
|
| H A D | mali_kbase_pm_driver.c | 915 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
936 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_disable_interrupts_nolock()
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_mmu_hw_direct.c | 373 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask, kctx); in kbase_mmu_hw_clear_fault()
|
| H A D | mali_kbase_irq_linux.c | 281 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val, NULL); in kbase_mmu_irq_test_handler()
|
| H A D | mali_kbase_pm_driver.c | 1022 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1045 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_disable_interrupts_nolock()
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_irq_linux.c | 314 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val); in kbase_mmu_irq_test_handler()
|
| H A D | mali_kbase_pm_driver.c | 1694 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
1720 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 256 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ macro
304 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 259 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ macro
308 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_irq_linux.c | 314 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val); in kbase_mmu_irq_test_handler()
|
| H A D | mali_kbase_pm_driver.c | 2243 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
2269 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
|
| H A D | mali_kbase_model_dummy.c | 1254 } else if (addr == MMU_REG(MMU_IRQ_CLEAR)) {
|
| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 200 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ macro
252 * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
|