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Searched refs:JOB_IRQ_MASK (Results 1 - 24 of 24) sorted by relevance

/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_dummy_job_wa.c176 old_job_mask = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)); in kbase_dummy_job_wa_execute()
178 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0); in kbase_dummy_job_wa_execute()
232 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), old_job_mask); in kbase_dummy_job_wa_execute()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_kbase_dummy_job_wa.c167 old_job_mask = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)); in kbase_dummy_job_wa_execute()
169 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0); in kbase_dummy_job_wa_execute()
225 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), old_job_mask); in kbase_dummy_job_wa_execute()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_debug_job_fault_backend.c34 static int job_control_reg_snapshot[] = {JOB_IRQ_MASK, JOB_IRQ_STATUS};
H A Dmali_kbase_irq_linux.c342 mask_offset = JOB_CONTROL_REG(JOB_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_pm_driver.c1692 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0xFFFFFFFF);
1716 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0);
H A Dmali_kbase_jm_hw.c950 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
951 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)), kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)), in kbase_debug_dump_registers()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_debug_job_fault_backend.c37 JOB_IRQ_MASK,
H A Dmali_kbase_irq_linux.c311 mask_offset = JOB_CONTROL_REG(JOB_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_pm_driver.c1020 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1040 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
H A Dmali_kbase_jm_hw.c1140 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
1142 kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), NULL), in kbase_debug_dump_registers()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_debug_job_fault_backend.c27 static int job_control_reg_snapshot[] = {JOB_IRQ_MASK, JOB_IRQ_STATUS};
H A Dmali_kbase_irq_linux.c302 mask_offset = JOB_CONTROL_REG(JOB_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_pm_driver.c913 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
932 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
H A Dmali_kbase_jm_hw.c1024 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
1026 kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), NULL), in kbase_debug_dump_registers()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_debug_job_fault_backend.c41 JOB_IRQ_MASK,
H A Dmali_kbase_model_dummy.c1158 } else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK)) {
1171 } else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK)) {
1172 /* ignore JOB_IRQ_MASK as it is handled by CSFFW */
1464 else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK)) {
1473 else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK)) {
1474 /* ignore JOB_IRQ_MASK as it is handled by CSFFW */
H A Dmali_kbase_irq_linux.c344 mask_offset = JOB_CONTROL_REG(JOB_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_pm_driver.c2241 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0xFFFFFFFF);
2265 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0);
H A Dmali_kbase_jm_hw.c1070 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
1072 kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)), in kbase_debug_dump_registers()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h171 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ macro
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_midg_regmap.h198 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ macro
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_midg_regmap.h205 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ macro
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_reset_gpu.c247 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_csf_debug_dump_registers()
249 kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)), in kbase_csf_debug_dump_registers()
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h191 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ macro

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