| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/ |
| H A D | mali_kbase_device_hw.c | 92 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_cache_flush_and_busy_wait()
95 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_cache_flush_and_busy_wait()
150 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_start_cache_clean_nolock()
151 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_start_cache_clean_nolock()
196 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_clean_caches_done()
197 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_clean_caches_done()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/ |
| H A D | mali_kbase_device_hw.c | 98 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_start_cache_clean_nolock()
99 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | CLEAN_CACHES_COMPLETED); in kbase_gpu_start_cache_clean_nolock()
139 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_clean_caches_done()
140 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~CLEAN_CACHES_COMPLETED); in kbase_clean_caches_done()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_instr_backend.c | 49 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbasep_instr_hwcnt_cacheclean()
50 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbasep_instr_hwcnt_cacheclean()
100 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbase_instr_hwcnt_enable_internal()
101 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | in kbase_instr_hwcnt_enable_internal()
232 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbase_instr_hwcnt_disable_internal()
233 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_instr_hwcnt_disable_internal()
397 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_clean_caches_done()
399 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_clean_caches_done()
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| H A D | mali_kbase_pm_driver.c | 1014 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), GPU_IRQ_REG_ALL, in kbase_pm_enable_interrupts()
1037 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
1407 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED, in kbase_pm_do_reset()
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| H A D | mali_kbase_jm_hw.c | 1140 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
1141 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL), in kbase_debug_dump_registers()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/ |
| H A D | mali_kbase_instr_backend.c | 44 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbasep_instr_hwcnt_cacheclean()
45 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | CLEAN_CACHES_COMPLETED, NULL); in kbasep_instr_hwcnt_cacheclean()
92 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbase_instr_hwcnt_enable_internal()
93 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | PRFCNT_SAMPLE_COMPLETED, NULL); in kbase_instr_hwcnt_enable_internal()
211 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbase_instr_hwcnt_disable_internal()
212 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~PRFCNT_SAMPLE_COMPLETED, NULL); in kbase_instr_hwcnt_disable_internal()
363 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbase_clean_caches_done()
364 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~CLEAN_CACHES_COMPLETED, NULL); in kbase_clean_caches_done()
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| H A D | mali_kbase_pm_driver.c | 909 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), GPU_IRQ_REG_ALL, NULL); in kbase_pm_enable_interrupts()
930 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
1274 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED, NULL); in kbase_pm_do_reset()
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| H A D | mali_kbase_jm_hw.c | 1024 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
1025 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL), in kbase_debug_dump_registers()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_pm_internal.h | 889 GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_pm_enable_db_mirror_interrupt()
893 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_pm_enable_db_mirror_interrupt()
913 GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_pm_disable_db_mirror_interrupt()
915 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_pm_disable_db_mirror_interrupt()
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| H A D | mali_kbase_instr_backend.c | 63 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_instr_hwcnt_enable_internal()
64 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | in kbase_instr_hwcnt_enable_internal()
134 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbasep_instr_hwc_disable_hw_prfcnt()
136 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~PRFCNT_SAMPLE_COMPLETED); in kbasep_instr_hwc_disable_hw_prfcnt()
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| H A D | mali_kbase_model_dummy.c | 1164 } else if (addr == GPU_CONTROL_REG(GPU_IRQ_MASK)) {
1173 } else if (addr == GPU_CONTROL_REG(GPU_IRQ_MASK)) {
1175 pr_debug("GPU_IRQ_MASK set to 0x%x", value);
1477 else if (addr == GPU_CONTROL_REG(GPU_IRQ_MASK)) {
1480 pr_debug("GPU_IRQ_MASK read %x", *value);
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| H A D | mali_kbase_pm_driver.c | 2237 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), GPU_IRQ_REG_ALL);
2263 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0);
2797 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED);
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| H A D | mali_kbase_jm_hw.c | 1070 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
1071 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)), in kbase_debug_dump_registers()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_instr_backend.c | 60 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_instr_hwcnt_enable_internal()
61 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | PRFCNT_SAMPLE_COMPLETED); in kbase_instr_hwcnt_enable_internal()
173 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_instr_hwcnt_disable_internal()
174 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~PRFCNT_SAMPLE_COMPLETED); in kbase_instr_hwcnt_disable_internal()
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| H A D | mali_kbase_pm_driver.c | 1688 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), GPU_IRQ_REG_ALL);
1714 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0);
2150 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), RESET_COMPLETED);
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| H A D | mali_kbase_jm_hw.c | 950 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_debug_dump_registers()
951 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)), kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)), in kbase_debug_dump_registers()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/ |
| H A D | mali_kbase_dummy_job_wa.c | 175 old_gpu_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_dummy_job_wa_execute()
177 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0); in kbase_dummy_job_wa_execute()
231 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), old_gpu_mask); in kbase_dummy_job_wa_execute()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/ |
| H A D | mali_kbase_dummy_job_wa.c | 166 old_gpu_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_dummy_job_wa_execute()
168 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0); in kbase_dummy_job_wa_execute()
224 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), old_gpu_mask); in kbase_dummy_job_wa_execute()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/backend/ |
| H A D | mali_kbase_device_hw_csf.c | 102 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_interrupt()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 45 #define GPU_IRQ_MASK 0x028 /* (RW) */ macro
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 37 #define GPU_IRQ_MASK 0x028 /* (RW) */ macro
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_midg_regmap.h | 41 #define GPU_IRQ_MASK 0x028 /* (RW) */ macro
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/ |
| H A D | mali_kbase_csf_reset_gpu.c | 247 dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x", in kbase_csf_debug_dump_registers()
248 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)), in kbase_csf_debug_dump_registers()
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| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/ |
| H A D | mali_kbase_gpu_regmap.h | 53 #define GPU_IRQ_MASK 0x028 /* (RW) */ macro
|