Searched refs:DCLK_VOP1 (Results 1 - 9 of 9) sorted by relevance
| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3288-cru.h | 88 #define DCLK_VOP1 191 macro
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| H A D | rk3568-cru.h | 287 #define DCLK_VOP1 224 macro
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| H A D | rk3399-cru.h | 140 #define DCLK_VOP1 181 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk3568-cru.h | 287 #define DCLK_VOP1 224 macro
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| H A D | rk3588-cru.h | 625 #define DCLK_VOP1 629 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3288.c | 330 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8,
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| H A D | clk-rk3399.c | 276 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 793 COMPOSITE_DCLK(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3588.c | 2076 COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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Completed in 26 milliseconds