Home
last modified time | relevance | path

Searched refs:CLK_SET_RATE_PARENT (Results 1 - 23 of 23) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c86 MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
87 DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
88 DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
90 FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT),
91 DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
92 DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
94 MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
95 DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
96 DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
98 FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT),
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c97 MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
98 DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
99 DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
101 FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT),
102 DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
103 DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
105 MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
106 DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
107 DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
109 FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT),
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3308.c173 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
176 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
179 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
182 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
185 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(23), 14, 2, MFLAGS);
188 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(8), 14, 2, MFLAGS);
191 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(2), 8, 2, MFLAGS);
194 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(46), 15, 1, MFLAGS);
197 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CON(52), 10,
201 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, RK3308_CLKSEL_CO
[all...]
H A Dclk-px30.c173 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
176 MUX(SCLK_I2S0_TX_MUX, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
179 MUX(SCLK_I2S0_RX_MUX, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
182 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
185 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
188 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
191 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
194 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
197 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
200 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CO
[all...]
H A Dclk-rk3328.c190 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
193 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
196 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
199 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
202 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
205 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
208 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
220 MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, RK3328_MISC_CON, 13, 1, MFLAGS),
221 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK3328_MISC_CON, 15, 1, MFLAGS),
244 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT, RK3328_CLKGATE_CO
[all...]
H A Dclk-rk3368.c248 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
251 MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
254 MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
257 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
260 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
263 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
266 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
275 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
335 COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(28), 0,
339 GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT, RK3368_CLKGATE_CO
[all...]
H A Dclk-rv1108.c158 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
161 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
164 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
167 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(5), 12, 2, MFLAGS);
170 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(6), 12, 2, MFLAGS);
173 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
176 MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, RV1108_MISC_CON, 13, 1, MFLAGS),
177 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, RV1108_MISC_CON, 15, 1, MFLAGS),
329 MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(32), 15, 1, MFLAGS),
330 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT, RV1108_CLKSEL_CO
[all...]
H A Dclk-rk3228.c175 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
178 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
181 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
184 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
187 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
193 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
221 MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, RK2928_MISC_CON, 13, 1, MFLAGS),
222 MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, RK2928_MISC_CON, 14, 1, MFLAGS),
223 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK2928_MISC_CO
[all...]
H A Dclk-rk3128.c167 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
170 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
173 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
176 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
179 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
182 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
211 MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, RK2928_MISC_CON, 15, 1, MFLAGS),
298 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(8), 0, RK2928_CLKGATE_CON(4),
300 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, RK2928_CLKGATE_CON(4), 6, GFLAGS),
304 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CO
[all...]
H A Dclk-rk3399.c245 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
248 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
251 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
254 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
257 SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(33), 8, 2, MFLAGS, uart_mux_idx);
260 SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(34), 8, 2, MFLAGS, uart_mux_idx);
263 SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(35), 8, 2, MFLAGS, uart_mux_idx);
266 SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(36), 8, 2, MFLAGS, uart_mux_idx);
269 MUXTBL(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, RK3399_PMU_CLKSEL_CON(5), 8, 2,
273 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CO
[all...]
H A Dclk-rk3288.c199 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
202 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
205 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
208 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
211 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
214 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
217 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
220 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
261 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
276 COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CO
[all...]
H A Dclk-rk3036.c153 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
156 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
159 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
162 MUX(SCLK_I2S_PRE, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
228 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(17), 0,
230 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(18), 0,
232 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(19), 0,
271 COMPOSITE_FRACMUX(SCLK_I2S_FRAC, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(7), 0,
275 GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT, RK2928_CLKGATE_CON(0), 14, GFLAGS),
298 MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CO
[all...]
H A Dclk-rk3188.c243 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
314 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
328 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(9), 0, RK2928_CLKGATE_CON(0),
496 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
499 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
554 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
594 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(7), 0, RK2928_CLKGATE_CON(0),
H A Dclk-half-divider.c47 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_half_divider_bestdiv()
H A Dclk-cpu.c278 init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; in rockchip_clk_register_cpuclk()
H A Dclk.c299 init.flags = child->flags | CLK_SET_RATE_PARENT; in rockchip_clk_register_frac_branch()
546 flags |= CLK_SET_RATE_PARENT; in rockchip_clk_register_branches()
H A Dclk-pll.c1247 init.flags = CLK_SET_RATE_PARENT; in rockchip_clk_register_pll()
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c195 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(39), 14, 2, MFLAGS);
198 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(42), 14, 2, MFLAGS);
201 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(45), 14, 2, MFLAGS);
204 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(48), 14, 2, MFLAGS);
207 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(51), 14, 2, MFLAGS);
210 MUX(0, "clk_uart6_mux", mux_uart6_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(54), 14, 2, MFLAGS);
213 MUX(0, "clk_uart7_mux", mux_uart7_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(57), 14, 2, MFLAGS);
216 MUX(0, "dclk_vopraw_mux", mux_dclk_vopraw_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(5), 14, 2, MFLAGS);
219 MUX(0, "dclk_voplite_mux", mux_dclk_voplite_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(7), 14, 2, MFLAGS);
222 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CO
[all...]
/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A Dclk-rk3568.c324 CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
327 CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
330 CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
333 CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
336 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
339 CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
342 CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
345 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
348 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
351 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT, RK3568_CLKSEL_CO
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-rk3588.c519 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
523 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
527 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
531 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
535 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
539 MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT,
543 MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT,
547 MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT,
551 MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT,
555 MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT,
[all...]
H A Dclk-link.c59 init.flags |= CLK_SET_RATE_PARENT; in register_clocks()
/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A Drockchip.h25 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ macro
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dclk-provider.h21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ macro
1018 #define clk_hw_can_set_rate_parent(hw) (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)

Completed in 21 milliseconds