Home
last modified time | relevance | path

Searched refs:BIT (Results 1 - 25 of 247) sorted by relevance

12345678910

/device/soc/rockchip/rk3588/kernel/drivers/net/ethernet/stmicro/stmmac/
H A Ddescs.h18 #define RDES0_PAYLOAD_CSUM_ERR BIT(0)
19 #define RDES0_CRC_ERROR BIT(1)
20 #define RDES0_DRIBBLING BIT(2)
21 #define RDES0_MII_ERROR BIT(3)
22 #define RDES0_RECEIVE_WATCHDOG BIT(4)
23 #define RDES0_FRAME_TYPE BIT(5)
24 #define RDES0_COLLISION BIT(6)
25 #define RDES0_IPC_CSUM_ERROR BIT(7)
26 #define RDES0_LAST_DESCRIPTOR BIT(8)
27 #define RDES0_FIRST_DESCRIPTOR BIT(
[all...]
/device/soc/rockchip/common/sdk_linux/include/dt-bindings/suspend/
H A Drockchip-rk3568.h13 #ifndef BIT
14 #define BIT(nr) (1 << (nr)) macro
17 #define RKPM_SLP_WFI BIT(0)
18 #define RKPM_SLP_ARMOFF BIT(1)
19 #define RKPM_SLP_CENTER_OFF BIT(2)
20 #define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
21 #define RKPM_SLP_FROM_UBOOT BIT(4)
22 #define RKPM_SLP_PMIC_LP BIT(5)
23 #define RKPM_SLP_HW_PLLS_OFF BIT(6)
24 #define RKPM_SLP_PMUALIVE_32K BIT(
[all...]
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/suspend/
H A Drockchip-rk3588.h13 #ifndef BIT
14 #define BIT(nr) (1 << (nr)) macro
17 #define RKPM_SLP_ARMPD BIT(0)
18 #define RKPM_SLP_ARMOFF BIT(1)
19 #define RKPM_SLP_ARMOFF_DDRPD BIT(2)
20 #define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
21 #define RKPM_SLP_ARMOFF_PMUOFF BIT(4)
24 #define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
25 #define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
26 #define RKPM_SLP_PMU_DIS_OSC BIT(1
[all...]
/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Dpm_domains.c1143 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), true),
1144 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
1145 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
1146 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(1
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/soc/rockchip/
H A Dpm_domains.c1156 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), true),
1157 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
1158 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
1159 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(1
[all...]
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/ispp/
H A Dregs.h328 #define FMT_YC_SWAP BIT(3)
329 #define FMT_YUYV BIT(2)
330 #define FMT_YUV422 BIT(1)
331 #define FMT_FBC BIT(0)
333 #define NR_NEW_ALGO BIT(16)
336 #define FEC_ST BIT(2)
337 #define NR_SHP_ST BIT(1)
338 #define TNR_ST BIT(0)
342 #define FEC_FORCE_UPD BIT(2)
343 #define TNR_FORCE_UPD BIT(
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/ispp/
H A Dregs.h328 #define FMT_YC_SWAP BIT(3)
329 #define FMT_YUYV BIT(2)
330 #define FMT_YUV422 BIT(1)
331 #define FMT_FBC BIT(0)
333 #define NR_NEW_ALGO BIT(16)
336 #define FEC_ST BIT(2)
337 #define NR_SHP_ST BIT(1)
338 #define TNR_ST BIT(0)
342 #define FEC_FORCE_UPD BIT(2)
343 #define TNR_FORCE_UPD BIT(
[all...]
/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A Drockchip.h5 #ifndef BIT
6 #define BIT(nr) (1 << (nr)) macro
10 #define CLK_DIVIDER_ONE_BASED BIT(0)
11 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
12 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
13 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
16 #define CLK_DIVIDER_USER_DEFINE BIT(7)
23 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
24 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_SET_RATE_PARENT BIT(
[all...]
/device/soc/rockchip/common/sdk_linux/include/linux/mfd/
H A Drk808.h294 #define RK816_IRQ_PWRON_FALL_MSK BIT(5)
295 #define RK816_IRQ_PWRON_RISE_MSK BIT(6)
296 #define RK816_IRQ_VB_LOW_MSK BIT(1)
297 #define RK816_IRQ_PWRON_MSK BIT(2)
298 #define RK816_IRQ_PWRON_LP_MSK BIT(3)
299 #define RK816_IRQ_HOTDIE_MSK BIT(4)
300 #define RK816_IRQ_RTC_ALARM_MSK BIT(5)
301 #define RK816_IRQ_RTC_PERIOD_MSK BIT(6)
302 #define RK816_IRQ_USB_OV_MSK BIT(7)
303 #define RK816_IRQ_PLUG_IN_MSK BIT(
[all...]
/device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/
H A Drockchip_iep2_regs.h15 #define IEP2_REG_CCLK_SRESET_P BIT(22)
16 #define IEP2_REG_ACLK_SRESET_P BIT(21)
17 #define IEP2_REG_HANDSAVE_P BIT(20)
18 #define IEP2_REG_RST_PROTECT_EN BIT(19)
19 #define IEP2_REG_DEBUG_DATA_EN BIT(16)
25 #define IEP2_REG_REG_CLK_ON BIT(11)
26 #define IEP2_REG_DMA_CLK_ON BIT(10)
27 #define IEP2_REG_RAM_CLK_ON BIT(9)
28 #define IEP2_REG_CTRL_CLK_ON BIT(8)
29 #define IEP2_REG_OUT_CLK_ON BIT(
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/
H A Drockchip_iep2_regs.h15 #define IEP2_REG_CCLK_SRESET_P BIT(22)
16 #define IEP2_REG_ACLK_SRESET_P BIT(21)
17 #define IEP2_REG_HANDSAVE_P BIT(20)
18 #define IEP2_REG_RST_PROTECT_EN BIT(19)
19 #define IEP2_REG_DEBUG_DATA_EN BIT(16)
25 #define IEP2_REG_REG_CLK_ON BIT(11)
26 #define IEP2_REG_DMA_CLK_ON BIT(10)
27 #define IEP2_REG_RAM_CLK_ON BIT(9)
28 #define IEP2_REG_CTRL_CLK_ON BIT(8)
29 #define IEP2_REG_OUT_CLK_ON BIT(
[all...]
/device/soc/rockchip/common/sdk_linux/include/linux/usb/
H A Dquirks.h12 #define USB_QUIRK_STRING_FETCH_255 BIT(0)
15 #define USB_QUIRK_RESET_RESUME BIT(1)
18 #define USB_QUIRK_NO_SET_INTF BIT(2)
21 #define USB_QUIRK_CONFIG_INTF_STRINGS BIT(3)
24 #define USB_QUIRK_RESET BIT(4)
28 #define USB_QUIRK_HONOR_BNUMINTERFACES BIT(5)
32 #define USB_QUIRK_DELAY_INIT BIT(6)
43 #define USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL BIT(7)
46 #define USB_QUIRK_DEVICE_QUALIFIER BIT(8)
49 #define USB_QUIRK_IGNORE_REMOTE_WAKEUP BIT(
[all...]
/device/soc/rockchip/rk3588/kernel/include/linux/phy/
H A Dphy-rockchip-usbdp.h21 #define DP_SINK_HPD_CFG BIT(11)
22 #define DP_SINK_HPD_SEL BIT(10)
23 #define DP_AUX_DIN_SEL BIT(9)
24 #define DP_AUX_DOUT_SEL BIT(8)
32 #define CMN_DP_LANE_MUX_N(n) BIT((n) + 4)
33 #define CMN_DP_LANE_EN_N(n) BIT(n)
41 #define CMN_DP_TX_LANE_SWAP_EN BIT(2)
44 #define CMN_ROPLL_SSC_EN BIT(1)
45 #define CMN_LCPLL_SSC_EN BIT(0)
48 #define CMN_ANA_LCPLL_LOCK_DONE BIT(
[all...]
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Ddev.h55 #define GRP_ID_SENSOR BIT(0)
56 #define GRP_ID_MIPIPHY BIT(1)
57 #define GRP_ID_ISP BIT(2)
58 #define GRP_ID_ISP_MP BIT(3)
59 #define GRP_ID_ISP_SP BIT(4)
60 #define GRP_ID_ISP_DMARX BIT(5)
61 #define GRP_ID_ISP_BRIDGE BIT(6)
62 #define GRP_ID_CSI BIT(7)
78 ISP_FRAME_END = BIT(0),
79 ISP_FRAME_IN = BIT(
[all...]
H A Dregs.h49 #define ISP_CIF_DATA_WIDTH_10B (BIT(13) | 3 << 29)
53 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
61 #define CIF_ISP_CTRL_ISP_INFORM_ENABLE BIT(4)
62 #define CIF_ISP_CTRL_ISP_GAMMA_IN_ENA BIT(6)
63 #define CIF_ISP_CTRL_ISP_AWB_ENA BIT(7)
64 #define CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT BIT(8)
65 #define CIF_ISP_CTRL_ISP_CFG_UPD BIT(9)
66 #define CIF_ISP_CTRL_ISP_GEN_CFG_UPD BIT(10)
67 #define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA BIT(11)
68 #define CIF_ISP_CTRL_ISP_FLASH_MODE_ENA BIT(1
[all...]
H A Dprocfs.c212 seq_printf(p, "%-10s %s(0x%x)\n", "SDG", (val & BIT(0x06)) ? "ON" : "OFF", val); in isp30_show()
216 seq_printf(p, "%-10s %s(0x%x) (gain: 0x%08x, 0x%08x)\n", "AWBGAIN", (val & BIT(0x07)) ? "ON" : "OFF", val, in isp30_show()
287 seq_printf(p, "%-10s %s(0x%x)\n", "BigMode", val & BIT(0x1C) ? "ON" : "OFF", val); in isp30_show()
301 "DEBUG2", val, !!(val & BIT(0x1F)), !!(val & BIT(0x1E)), (val >> 0x10) & 0x3fff, (val >> 0x0E) & 0x3, in isp30_show()
310 "DEBUG3", val, !!(val & BIT(0x1F)), !!(val & BIT(0x1E)), !!(val & BIT(0x1D)), !!(val & BIT(0x1C)), in isp30_show()
311 !!(val & BIT( in isp30_show()
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Ddev.h53 #define GRP_ID_SENSOR BIT(0)
54 #define GRP_ID_MIPIPHY BIT(1)
55 #define GRP_ID_ISP BIT(2)
56 #define GRP_ID_ISP_MP BIT(3)
57 #define GRP_ID_ISP_SP BIT(4)
58 #define GRP_ID_ISP_DMARX BIT(5)
59 #define GRP_ID_ISP_BRIDGE BIT(6)
60 #define GRP_ID_CSI BIT(7)
71 ISP_FRAME_END = BIT(0),
72 ISP_FRAME_IN = BIT(
[all...]
H A Dregs.h52 #define ISP_CIF_DATA_WIDTH_10B (BIT(13) | 3 << 29)
56 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
64 #define CIF_ISP_CTRL_ISP_INFORM_ENABLE BIT(4)
65 #define CIF_ISP_CTRL_ISP_GAMMA_IN_ENA BIT(6)
66 #define CIF_ISP_CTRL_ISP_AWB_ENA BIT(7)
67 #define CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT BIT(8)
68 #define CIF_ISP_CTRL_ISP_CFG_UPD BIT(9)
69 #define CIF_ISP_CTRL_ISP_GEN_CFG_UPD BIT(10)
70 #define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA BIT(11)
71 #define CIF_ISP_CTRL_ISP_FLASH_MODE_ENA BIT(1
[all...]
/device/soc/rockchip/common/vendor/drivers/mmc/host/
H A Drk_sdmmc.h139 #define SDMMC_CTRL_USE_IDMAC BIT(25)
140 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
141 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
142 #define SDMMC_CTRL_SEND_CCSD BIT(9)
143 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
144 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
145 #define SDMMC_CTRL_READ_WAIT BIT(6)
146 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
147 #define SDMMC_CTRL_INT_ENABLE BIT(4)
148 #define SDMMC_CTRL_DMA_RESET BIT(
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/mmc/host/
H A Drk_sdmmc.h139 #define SDMMC_CTRL_USE_IDMAC BIT(25)
140 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
141 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
142 #define SDMMC_CTRL_SEND_CCSD BIT(9)
143 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
144 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
145 #define SDMMC_CTRL_READ_WAIT BIT(6)
146 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
147 #define SDMMC_CTRL_INT_ENABLE BIT(4)
148 #define SDMMC_CTRL_DMA_RESET BIT(
[all...]
H A Ddw_mmc.h337 #define SDMMC_CTRL_USE_IDMAC BIT(25)
338 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
339 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
340 #define SDMMC_CTRL_SEND_CCSD BIT(9)
341 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
342 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
343 #define SDMMC_CTRL_READ_WAIT BIT(6)
344 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
345 #define SDMMC_CTRL_INT_ENABLE BIT(4)
346 #define SDMMC_CTRL_DMA_RESET BIT(
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/mmc/host/
H A Drk_sdmmc.h157 #define SDMMC_CTRL_USE_IDMAC BIT(25)
158 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
159 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
160 #define SDMMC_CTRL_SEND_CCSD BIT(9)
161 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
162 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
163 #define SDMMC_CTRL_READ_WAIT BIT(6)
164 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
165 #define SDMMC_CTRL_INT_ENABLE BIT(4)
166 #define SDMMC_CTRL_DMA_RESET BIT(
[all...]
/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dtimer.h36 #define TIMER0_ENABLE BIT(16)
37 #define TIMER1_ENABLE BIT(17)
38 #define TIMER2_ENABLE BIT(18)
39 #define TIMER3_ENABLE BIT(19)
40 #define TIMER4_ENABLE BIT(20)
41 #define TIMER5_ENABLE BIT(21)
42 #define TIMER6_ENABLE BIT(22)
43 #define TIMER7_ENABLE BIT(23)
44 #define TIMER8_ENABLE BIT(24)
45 #define TIMER9_ENABLE BIT(2
[all...]
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dtimer.h36 #define TIMER0_ENABLE BIT(16)
37 #define TIMER1_ENABLE BIT(17)
38 #define TIMER2_ENABLE BIT(18)
39 #define TIMER3_ENABLE BIT(19)
40 #define TIMER4_ENABLE BIT(20)
41 #define TIMER5_ENABLE BIT(21)
42 #define TIMER6_ENABLE BIT(22)
43 #define TIMER7_ENABLE BIT(23)
44 #define TIMER8_ENABLE BIT(24)
45 #define TIMER9_ENABLE BIT(2
[all...]
/device/soc/hisilicon/common/platform/i2c/
H A Di2c_hi35xx.h47 #ifndef BIT
48 #define BIT(n) (1U << (n)) macro
53 #define GLB_EN_MASK BIT(0)
78 #define CTRL1_CMD_START_MASK BIT(0)
79 #define CTRL1_DMA_MASK (BIT(9) | BIT(8))
80 #define CTRL1_DMA_R (BIT(9) | BIT(8))
81 #define CTRL1_DMA_W (BIT(9))
86 #define STAT_RXF_NOE_MASK BIT(1
[all...]

Completed in 42 milliseconds

12345678910